Change in coreboot[master]: nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49755 )

Change subject: nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors
......................................................................

nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: Ic390d3431e2aa9f5f59cb266d4c358d0eb48576c
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49755
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/acpi/pineview.asl
M src/northbridge/intel/pineview/early_init.c
D src/northbridge/intel/pineview/memmap.h
M src/northbridge/intel/pineview/pineview.h
5 files changed, 19 insertions(+), 38 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index ad134f2..0ff437a 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -31,4 +31,13 @@
    hex
    default 0x80000

+config FIXED_MCHBAR_MMIO_BASE
+	default 0xfed14000
+
+config FIXED_DMIBAR_MMIO_BASE
+	default 0xfed18000
+
+config FIXED_EPBAR_MMIO_BASE
+	default 0xfed19000
+
 endif
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl
index 7db1d37..4b74469 100644
--- a/src/northbridge/intel/pineview/acpi/pineview.asl
+++ b/src/northbridge/intel/pineview/acpi/pineview.asl
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include "hostbridge.asl"
-#include "../memmap.h"

/* PCI Device Resource Consumption */
 Device (PDRC)
@@ -13,9 +12,9 @@

Name (PDRS, ResourceTemplate() {
    	Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
-		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
-		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
-		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE,  0x00001000)
    	Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
    	Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
    	Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 42a68d8..ce23984 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -136,9 +136,9 @@
    pci_write_config8(HOST_BRIDGE, 0x08, 0x69);

/* Set up all hardcoded northbridge BARs */
-	pci_write_config32(HOST_BRIDGE, EPBAR,   DEFAULT_EPBAR   | 1);
-	pci_write_config32(HOST_BRIDGE, MCHBAR,  DEFAULT_MCHBAR  | 1);
-	pci_write_config32(HOST_BRIDGE, DMIBAR,  DEFAULT_DMIBAR  | 1);
+	pci_write_config32(HOST_BRIDGE, EPBAR,  CONFIG_FIXED_EPBAR_MMIO_BASE  | 1);
+	pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
+	pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
    pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1);

/* Set C0000-FFFFF to access RAM on both reads and writes */
diff --git a/src/northbridge/intel/pineview/memmap.h b/src/northbridge/intel/pineview/memmap.h
deleted file mode 100644
index 50ede0b..0000000
--- a/src/northbridge/intel/pineview/memmap.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef PINEVIEW_MEMMAP_H
-#define PINEVIEW_MEMMAP_H
-
-#define DEFAULT_MCHBAR		0xfed14000	/* 16 KB */
-#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
-#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
-#define DEFAULT_PMIOBAR		0x00000400
-
-#endif /* PINEVIEW_MEMMAP_H */
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index a5bef59..914c3a3 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -3,9 +3,10 @@
 #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H
 #define NORTHBRIDGE_INTEL_PINEVIEW_H

-#include <northbridge/intel/pineview/memmap.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>

+#define DEFAULT_PMIOBAR		0x00000400
+
 #define BOOT_PATH_NORMAL	0
 #define BOOT_PATH_RESET		1
 #define BOOT_PATH_RESUME	2
@@ -32,9 +33,8 @@
  * MCHBAR
  */

-#define MCHBAR8(x)  (*((volatile u8  *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#include <northbridge/intel/common/fixed_bars.h>
+
 #define MCHBAR8_AND(x,  and) (MCHBAR8(x)  = MCHBAR8(x)  & (and))
 #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
 #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
@@ -49,22 +49,6 @@

#include "mchbar_regs.h"

-/*
- * EPBAR - Egress Port Root Complex Register Block
- */
-
-#define EPBAR8(x)  (*((volatile u8  *)(DEFAULT_EPBAR + (x))))
-#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
-#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
-
-/*
- * DMIBAR
- */
-
-#define DMIBAR8(x)  (*((volatile u8  *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
-
 void pineview_early_init(void);
 u32 decode_igd_memory_size(const u32 gms);
 u32 decode_igd_gtt_size(const u32 gsm);