Change in coreboot[master]: mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58853 )

Change subject: mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree
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mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree

PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on
this mainboard and are not routed either, so remove them from the
devicetree completely. PCIe root port #7 (00:1c.6) is connected and
used. Add the missing settings for L1 substates and latency reporting to
disable these features for this port as well.

Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49
Signed-off-by: Mario Scheithauer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853
Tested-by: build bot (Jenkins) 
Reviewed-by: Werner Zeh 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 2 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 8b9e9e2..701efb4 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -50,9 +50,7 @@
    register "PcieRpEnable[0]" = "1"
    register "PcieRpEnable[1]" = "1"
    register "PcieRpEnable[2]" = "1"
-	register "PcieRpEnable[3]" = "1"
    register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
    register "PcieRpEnable[6]" = "1"

register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
@@ -73,17 +71,15 @@
    register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
    register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
    register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
-	register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
    register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
-	register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"

# Disable LTR for all PCIe root ports
    register "PcieRpLtrDisable[0]" = "true"
    register "PcieRpLtrDisable[1]" = "true"
    register "PcieRpLtrDisable[2]" = "true"
-	register "PcieRpLtrDisable[3]" = "true"
    register "PcieRpLtrDisable[4]" = "true"
-	register "PcieRpLtrDisable[5]" = "true"
+	register "PcieRpLtrDisable[6]" = "true"

# Storage (SATA/SDCARD/EMMC) related UPDs
    register "SataSalpSupport" = "0"
@@ -220,9 +216,7 @@
    	device pci 1c.0 on	end # RP1 (pcie0 single VC)
    	device pci 1c.1 on	end # RP2 (pcie0 single VC)
    	device pci 1c.2 on	end # RP3 (pcie0 single VC)
-		device pci 1c.3 on	end # RP4 (pcie0 single VC)
    	device pci 1c.4 on	end # RP5 (pcie1 multi VC)
-		device pci 1c.5 on	end # RP6 (pcie2 multi VC)
    	device pci 1c.6 on	end # RP7 (pcie3 multi VC)

device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)