Hello Saurabh Mishra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84178?usp=email
to look at the new patch set (#2).
Change subject: src/soc/intel/cmn/block/inc: Add Extended Feature Enable Register Macro ......................................................................
src/soc/intel/cmn/block/inc: Add Extended Feature Enable Register Macro
Details: - Add (POWER_CTL) – Offset 1fc required bits.
Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/soc/intel/common/block/include/intelblocks/msr.h 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/84178/2