Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80550?usp=email )
Change subject: soc/intel/xeon_sp/uncore: Read VtdBar ......................................................................
soc/intel/xeon_sp/uncore: Read VtdBar
Read the VtdBar and add it to the resources of the host bridge PCI device. The BAR is already marked as PciResourceMem32 in the parent PCI domain. This allows easy probing for VTD devices with enabled VtdBars in the next commit, without the need to look up the stack HOB.
Change-Id: Id579a94e653473f3dd0dccea6e33dc64f792d028 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/80550 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 4 files changed, 19 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index d64a0d7..587c97c 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -114,6 +114,7 @@ #define VTD_CAP_LOW 0x08 #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 +#define VTD_BAR_CSR 0x180 #define VTD_LTDPR 0x290
/* IMC Devices */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index a5f2f8e..d317d0c 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -108,6 +108,7 @@ #define VTD_CAP_LOW 0x08 #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 +#define VTD_BAR_CSR 0x180 #define VTD_LTDPR 0x290
#define PCU_CR1_C2C3TT_REG 0xdc diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 9bbe540..158352a 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -136,6 +136,7 @@ #define VTD_MMIOL_CSR 0xd8 #define VTD_NCMEM_BASE_CSR 0xe0 #define VTD_NCMEM_LIMIT_CSR 0xe8 +#define VTD_BAR_CSR 0x180 #define VTD_LTDPR 0x290
#define VMD_DEV_NUM 0x00 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index d43b209..952ca4d 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -45,6 +45,7 @@ ME_LIMIT_REG, TSEG_BASE_REG, TSEG_LIMIT_REG, + VTDBAR_REG, /* Must be last. */ NUM_MAP_ENTRIES }; @@ -64,6 +65,7 @@ #endif [TSEG_BASE_REG] = MAP_ENTRY_BASE_32(VTD_TSEG_BASE_CSR, "TSEGMB_BASE"), [TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"), + [VTDBAR_REG] = MAP_ENTRY_BASE_32(VTD_BAR_CSR, "VTD_BAR"), };
static void read_map_entry(struct device *dev, struct map_entry *entry, @@ -76,6 +78,11 @@ *result = 0; return; } + if (entry->reg == VTD_BAR_CSR && !(pci_read_config32(dev, entry->reg) & 1)) { + /* VTDBAR is not enabled */ + *result = 0; + return; + }
mask = ((1ULL << entry->mask_bits) - 1); mask = ~mask; @@ -198,14 +205,19 @@ int index = *res_count; struct range_entry fsp_mem;
- /* Only add dram resources once. */ - if (dev->upstream->secondary != 0 || dev->upstream->segment_group != 0) - return; - /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]);
+ if (mc_values[VTDBAR_REG]) { + res = mmio_range(dev, VTD_BAR_CSR, mc_values[VTDBAR_REG], 8 * KiB); + LOG_RESOURCE("vtd_bar", dev, res); + } + + /* Only add dram resources once. */ + if (dev->upstream->secondary != 0 || dev->upstream->segment_group != 0) + return; + /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ res = ram_from_to(dev, index++, 0, 0xa0000); LOG_RESOURCE("legacy_ram", dev, res);