Change in coreboot[master]: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads

[Evgeny Zinoviev (Code Review)]

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59527 )

Change subject: mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
......................................................................

mb/lenovo: Enable MEI on Sandy Bridge ThinkPads

It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.

On X220, it was disabled by 0793afe9. I can't reproduce those issues
today.

Also:
- it breaks the me_disable feature,
- we already have a Kconfig option to hide MEI in case of errors,
- it will be hidden on disabled, recovery, firmware update paths anyway.

Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev 
---
M src/mainboard/lenovo/t420/devicetree.cb
M src/mainboard/lenovo/t420s/devicetree.cb
M src/mainboard/lenovo/x220/devicetree.cb
A src/southbridge/intel/bd82x6x/me_reset.c
4 files changed, 31 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/59527/1

diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index e42e519..457ccbe 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -61,7 +61,7 @@
    		register "spi_uvscc" = "0x2005"
    		register "spi_lvscc" = "0x2005"

-			device pci 16.0 off end # Management Engine Interface 1
+			device pci 16.0 on  end # Management Engine Interface 1
    		device pci 16.1 off end # Management Engine Interface 2
    		device pci 16.2 off end # Management Engine IDE-R
    		device pci 16.3 off end # Management Engine KT
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index ab98ca0..32736a8 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -63,7 +63,7 @@
    		register "spi_uvscc" = "0x2005"
    		register "spi_lvscc" = "0x2005"

-			device pci 16.0 off end # Management Engine Interface 1
+			device pci 16.0 on  end # Management Engine Interface 1
    		device pci 16.1 off end # Management Engine Interface 2
    		device pci 16.2 off end # Management Engine IDE-R
    		device pci 16.3 off end # Management Engine KT
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 53eb23a..b239d64 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -60,7 +60,7 @@
    		register "spi_uvscc" = "0x2005"
    		register "spi_lvscc" = "0x2005"

-			device pci 16.0 off end # Management Engine Interface 1
+			device pci 16.0 on  end # Management Engine Interface 1
    		device pci 16.1 off end # Management Engine Interface 2
    		device pci 16.2 off end # Management Engine IDE-R
    		device pci 16.3 off end # Management Engine KT
diff --git a/src/southbridge/intel/bd82x6x/me_reset.c b/src/southbridge/intel/bd82x6x/me_reset.c
new file mode 100644
index 0000000..4b9fef7
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/me_reset.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+void set_global_reset(bool enable)
+{
+#ifdef __SIMPLE_DEVICE__
+	u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+#else
+	struct device *lpc = pcidev_on_root(0x1f, 0);
+	u32 etr3 = pci_read_config32(lpc, ETR3);
+#endif
+
+	/* Clear CF9 Without Resume Well Reset Enable */
+	etr3 &= ~ETR3_CWORWRE;
+
+	/* CF9GR indicates a Global Reset */
+	if (enable)
+		etr3 |= ETR3_CF9GR;
+	else
+		etr3 &= ~ETR3_CF9GR;
+
+#ifdef __SIMPLE_DEVICE__
+	pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+#else
+	pci_write_config32(lpc, ETR3, etr3);
+#endif
+}