Change in coreboot[master]: cpu/haswell/*.c: Use static.c exposed lapic 0

[Raul Rangel (Code Review)]

Attention is currently required from: Arthur Heymans, Tristan Corrick, Angel Pons, Alexander Couzens, Patrick Rudolph.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59314 )

Change subject: cpu/haswell/*.c: Use static.c exposed lapic 0
......................................................................

Patch Set 2: Code-Review+1

(1 comment)

File src/mainboard/google/auron/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/59314/comment/391aa047_24e47381 
PS2, Line 20: 			device lapic 0xacac off end
Going back to my original question. Why do we need the lapic to hold the config?

Right now it looks like the structure is:

```
chip soc/intel/broadwell
    device cpu_cluster 0 on
        chip cpu/intel/haswell
            register "s0ix_enable" = "1"
            device lapic 0 on end
        end
    end
end
```

The problem was that we can't have 2 chips apply to the same device. We don't need to have the cpu_cluster nested under the soc chip do we? Does the following work?

```
chip cpu/intel/haswell
    register "s0ix_enable" = "1"
    device cpu_cluster 0 on
        device lapic 0 on end <- I think you could optionally get rid of this now
    end
end

chip soc/intel/broadwell
    ...
    device domain 0 on
        ....
    end
    ...
end
```

I'm not going to block this CL or anything, just throwing out ideas.