Change in coreboot[master]: soc/amd/stoneyridge: unify and align include guards with picasso
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47582 )
Change subject: soc/amd/stoneyridge: unify and align include guards with picasso ......................................................................
soc/amd/stoneyridge: unify and align include guards with picasso
Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/stoneyridge/include/soc/acpi.h M src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h M src/soc/amd/stoneyridge/include/soc/cpu.h M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/romstage.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 11 files changed, 33 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47582/1
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 9617b45..19f0c81 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOC_STONEYRIDGE_ACPI_H__ -#define __SOC_STONEYRIDGE_ACPI_H__ +#ifndef AMD_STONEYRIDGE_ACPI_H +#define AMD_STONEYRIDGE_ACPI_H
#include <acpi/acpi.h>
@@ -16,4 +16,4 @@
const char *soc_acpi_name(const struct device *dev);
-#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ +#endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index c327863..3b54076 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H +#define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
/* * PIRQ and device routing - these define the index into the @@ -44,4 +44,4 @@ #define PIRQ_UART0 0x74 #define PIRQ_UART1 0x75
-#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index 8d25fb6..528daa4 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_CPU_H__ -#define __STONEYRIDGE_CPU_H__ +#ifndef AMD_STONEYRIDGE_CPU_H +#define AMD_STONEYRIDGE_CPU_H
/* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest @@ -16,4 +16,4 @@
void check_mca(void);
-#endif /* __STONEYRIDGE_CPU_H__ */ +#endif /* AMD_STONEYRIDGE_CPU_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 02cc188..8bfb1f6 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_GPIO_H__ -#define __STONEYRIDGE_GPIO_H__ +#ifndef AMD_STONEYRIDGE_GPIO_H +#define AMD_STONEYRIDGE_GPIO_H
#define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -292,4 +292,4 @@ #define GPIO_2_EVENT GEVENT_8
#endif /* __ACPI__ */ -#endif /* __STONEYRIDGE_GPIO_H__ */ +#endif /* AMD_STONEYRIDGE_GPIO_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 63db7d4..0b61329 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_I2C_H__ -#define __STONEYRIDGE_I2C_H__ +#ifndef AMD_STONEYRIDGE_I2C_H +#define AMD_STONEYRIDGE_I2C_H
#include <types.h> #include <soc/gpio.h> @@ -29,4 +29,4 @@
void sb_reset_i2c_slaves(void);
-#endif /* __STONEYRIDGE_I2C_H__ */ +#endif /* AMD_STONEYRIDGE_I2C_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 8056287..4328880 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_STONEYRIDGE_IOMAP_H__ -#define __SOC_STONEYRIDGE_IOMAP_H__ +#ifndef AMD_STONEYRIDGE_IOMAP_H +#define AMD_STONEYRIDGE_IOMAP_H
/* MMIO Ranges */ #define PSP_MAILBOX_BAR3_BASE 0xf0a00000 @@ -51,4 +51,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
-#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ +#endif /* AMD_STONEYRIDGE_IOMAP_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 3b5fd22..d00f566 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ -#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#ifndef AMD_STONEYRIDGE_NORTHBRIDGE_H +#define AMD_STONEYRIDGE_NORTHBRIDGE_H
#include <device/device.h> #include <types.h> @@ -89,4 +89,4 @@ void set_warm_reset_flag(void); int is_warm_reset(void);
-#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 03a1233..6af657f 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ -#define __PI_STONEYRIDGE_PCI_DEVS_H__ +#ifndef AMD_STONEYRIDGE_PCI_DEVS_H +#define AMD_STONEYRIDGE_PCI_DEVS_H
#include <device/pci_def.h> #include <amdblocks/pci_devs.h> @@ -201,4 +201,4 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC)
-#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ +#endif /* AMD_STONEYRIDGE_PCI_DEVS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 6dc0b72..1cbaeec 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_ROMSTAGE_H__ -#define __STONEYRIDGE_ROMSTAGE_H__ +#ifndef AMD_STONEYRIDGE_ROMSTAGE_H +#define AMD_STONEYRIDGE_ROMSTAGE_H
void mainboard_romstage_entry_s3(int s3_resume);
-#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ +#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 15bba0f..60a91d0 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#ifndef AMD_STONEYRIDGE_SMI_H +#define AMD_STONEYRIDGE_SMI_H
#define SMI_GEVENTS 24 #define SCIMAPS 58 @@ -218,4 +218,4 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ +#endif /* AMD_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 85df0b3..cbd9caa 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_H__ -#define __STONEYRIDGE_H__ +#ifndef AMD_STONEYRIDGE_SOUTHBRIDGE_H +#define AMD_STONEYRIDGE_SOUTHBRIDGE_H
#include <types.h> #include <device/device.h> @@ -349,4 +349,4 @@ /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void);
-#endif /* __STONEYRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47582 )
Change subject: soc/amd/stoneyridge: unify and align include guards with picasso ......................................................................
Patch Set 1:
See CB:21073, I have no access to BUG=b:62235990 commentary.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47582 )
Change subject: soc/amd/stoneyridge: unify and align include guards with picasso ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47582 )
Change subject: soc/amd/stoneyridge: unify and align include guards with picasso ......................................................................
soc/amd/stoneyridge: unify and align include guards with picasso
Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/47582 Reviewed-by: Martin Roth martinroth@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/stoneyridge/include/soc/acpi.h M src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h M src/soc/amd/stoneyridge/include/soc/cpu.h M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/romstage.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 11 files changed, 33 insertions(+), 33 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 9617b45..19f0c81 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOC_STONEYRIDGE_ACPI_H__ -#define __SOC_STONEYRIDGE_ACPI_H__ +#ifndef AMD_STONEYRIDGE_ACPI_H +#define AMD_STONEYRIDGE_ACPI_H
#include <acpi/acpi.h>
@@ -16,4 +16,4 @@
const char *soc_acpi_name(const struct device *dev);
-#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ +#endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index c327863..3b54076 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H +#define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
/* * PIRQ and device routing - these define the index into the @@ -44,4 +44,4 @@ #define PIRQ_UART0 0x74 #define PIRQ_UART1 0x75
-#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index 8d25fb6..528daa4 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_CPU_H__ -#define __STONEYRIDGE_CPU_H__ +#ifndef AMD_STONEYRIDGE_CPU_H +#define AMD_STONEYRIDGE_CPU_H
/* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest @@ -16,4 +16,4 @@
void check_mca(void);
-#endif /* __STONEYRIDGE_CPU_H__ */ +#endif /* AMD_STONEYRIDGE_CPU_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 02cc188..8bfb1f6 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_GPIO_H__ -#define __STONEYRIDGE_GPIO_H__ +#ifndef AMD_STONEYRIDGE_GPIO_H +#define AMD_STONEYRIDGE_GPIO_H
#define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -292,4 +292,4 @@ #define GPIO_2_EVENT GEVENT_8
#endif /* __ACPI__ */ -#endif /* __STONEYRIDGE_GPIO_H__ */ +#endif /* AMD_STONEYRIDGE_GPIO_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 63db7d4..0b61329 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_I2C_H__ -#define __STONEYRIDGE_I2C_H__ +#ifndef AMD_STONEYRIDGE_I2C_H +#define AMD_STONEYRIDGE_I2C_H
#include <types.h> #include <soc/gpio.h> @@ -29,4 +29,4 @@
void sb_reset_i2c_slaves(void);
-#endif /* __STONEYRIDGE_I2C_H__ */ +#endif /* AMD_STONEYRIDGE_I2C_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 8056287..4328880 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_STONEYRIDGE_IOMAP_H__ -#define __SOC_STONEYRIDGE_IOMAP_H__ +#ifndef AMD_STONEYRIDGE_IOMAP_H +#define AMD_STONEYRIDGE_IOMAP_H
/* MMIO Ranges */ #define PSP_MAILBOX_BAR3_BASE 0xf0a00000 @@ -51,4 +51,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
-#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ +#endif /* AMD_STONEYRIDGE_IOMAP_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 3b5fd22..d00f566 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ -#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#ifndef AMD_STONEYRIDGE_NORTHBRIDGE_H +#define AMD_STONEYRIDGE_NORTHBRIDGE_H
#include <device/device.h> #include <types.h> @@ -89,4 +89,4 @@ void set_warm_reset_flag(void); int is_warm_reset(void);
-#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 03a1233..6af657f 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ -#define __PI_STONEYRIDGE_PCI_DEVS_H__ +#ifndef AMD_STONEYRIDGE_PCI_DEVS_H +#define AMD_STONEYRIDGE_PCI_DEVS_H
#include <device/pci_def.h> #include <amdblocks/pci_devs.h> @@ -201,4 +201,4 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC)
-#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ +#endif /* AMD_STONEYRIDGE_PCI_DEVS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 6dc0b72..1cbaeec 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_ROMSTAGE_H__ -#define __STONEYRIDGE_ROMSTAGE_H__ +#ifndef AMD_STONEYRIDGE_ROMSTAGE_H +#define AMD_STONEYRIDGE_ROMSTAGE_H
void mainboard_romstage_entry_s3(int s3_resume);
-#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ +#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 15bba0f..60a91d0 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#ifndef AMD_STONEYRIDGE_SMI_H +#define AMD_STONEYRIDGE_SMI_H
#define SMI_GEVENTS 24 #define SCIMAPS 58 @@ -218,4 +218,4 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event);
-#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ +#endif /* AMD_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 85df0b3..cbd9caa 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __STONEYRIDGE_H__ -#define __STONEYRIDGE_H__ +#ifndef AMD_STONEYRIDGE_SOUTHBRIDGE_H +#define AMD_STONEYRIDGE_SOUTHBRIDGE_H
#include <types.h> #include <device/device.h> @@ -349,4 +349,4 @@ /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void);
-#endif /* __STONEYRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */
-
Felix Held (Code Review) -
Kyösti Mälkki (Code Review)
-
Martin Roth (Code Review)