[S] Change in coreboot[main]: soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83865?usp=email )

Change subject: soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning
......................................................................

soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning

If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:

Found overlapped clkreq assignment on clk req 0

Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file

Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
Reviewed-by: Maximilian Brune 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 10 insertions(+), 6 deletions(-)

Approvals:
  Maximilian Brune: Looks good to me, approved
  Matt DeVillier: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index d917e6c..a63b64c 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -71,10 +71,12 @@
    		printk(BIOS_WARNING, "Missing root port clock structure definition\n");
    		continue;
    	}
-		if (clk_req_mapping & (1 << cfg[i].clk_req))
-			printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
-				, cfg[i].clk_req);
+
    	if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
+			if (clk_req_mapping & (1 << cfg[i].clk_req))
+				printk(BIOS_WARNING,
+				       "Found overlapped clkreq assignment on clk req %d\n",
+				       cfg[i].clk_req);
    		m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
    		clk_req_mapping |= 1 << cfg[i].clk_req;
    	}
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 9734c63..055fec7 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -52,10 +52,12 @@
    		printk(BIOS_WARNING, "Missing root port clock structure definition\n");
    		continue;
    	}
-		if (clk_req_mapping & (1 << cfg[i].clk_req))
-			printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
-				, cfg[i].clk_req);
+
    	if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
+			if (clk_req_mapping & (1 << cfg[i].clk_req))
+				printk(BIOS_WARNING,
+				       "Found overlapped clkreq assignment on clk req %d\n",
+				       cfg[i].clk_req);
    		m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
    		clk_req_mapping |= 1 << cfg[i].clk_req;
    	}