Change in coreboot[master]: mb/google/brya/var/banshee: add the smbus addr for dimm1

[Frank Wu (Code Review)]

Attention is currently required from: John Su, YH Lin, Dtrain Hsu, Ian Feng, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Amanda Hwang, Zhuohao Lee.
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63622 )

Change subject: mb/google/brya/var/banshee: add the smbus addr for dimm1
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> Please elaborate why MRC training again. IIUC, banshee only have 2 MC.

[INFO ]  MRC: Hash idx 0x100d comparison successful.
[SPEW ]  MRC cache found, size f6c8
[SPEW ]  bootmode is set to: 2
[DEBUG]  FMAP: area RW_SPD_CACHE found @ f28000 (4096 bytes)
[INFO ]  SPD_CACHE: cache found, size 0x1000
[NOTE ]  SPD_CACHE: DIMM0 is the same
[INFO ]  DIMM change, invalidate cache.
[DEBUG]  FMAP: area RW_SPD_CACHE found @ f28000 (4096 bytes)
[SPEW ]  Erasing flash addr f28000 + 4 KiB
[INFO ]  SPD: module type is DDR4
[INFO ]  SPD: module part number is M471A1K43EB1-CWE    
[INFO ]  SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb
[INFO ]  SPD: device width 8 bits, bus width 64 bits
[INFO ]  SPD: module size is 8192 MB (per channel)
[INFO ]  SPD: module type is DDR4
[INFO ]  SPD: module part number is M471A1K43EB1-CWE    
[INFO ]  SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb
[INFO ]  SPD: device width 8 bits, bus width 64 bits
[INFO ]  SPD: module size is 8192 MB (per channel)