Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
sb/intel/i82801gx/fadt.c: Align with i82801ix
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: I930de15a6746936fa4a8f6db280b5ac60176c836 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801gx/fadt.c 1 file changed, 7 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42652/1
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index abf31c3..d6ff380 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -35,7 +35,8 @@ fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; @@ -53,7 +54,7 @@ fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->iapc_boot_arch = 0x03; + fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER @@ -61,14 +62,13 @@ if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
- fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; + fadt->reset_value = 0x06;
fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; @@ -85,7 +85,8 @@ fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... PS1, Line 38: /* Upper word is reserved and : Linux complains about 32 bit. */ Number of bytes decoded by PM1a_CNT_BLK and, if supported, PM1b_CNT_BLK. This value is >= 2.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... PS1, Line 38: /* Upper word is reserved and : Linux complains about 32 bit. */
Number of bytes decoded by PM1a_CNT_BLK and, if supported, PM1b_CNT_BLK. […]
So, the comment is wrong?
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42652
to look at the new patch set (#2).
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
sb/intel/i82801gx/fadt.c: Align with i82801ix
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: I930de15a6746936fa4a8f6db280b5ac60176c836 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801gx/fadt.c 1 file changed, 18 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42652/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... PS1, Line 38: /* Upper word is reserved and : Linux complains about 32 bit. */
So, the comment is wrong?
Yes, I think
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... PS1, Line 38: /* Upper word is reserved and : Linux complains about 32 bit. */
Yes, I think
Origins of the comment: https://review.coreboot.org/1691
The code is the same, if the comment is wrong it likely applies to all three southbridges
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/42652/1/src/southbridge/intel/i8280... PS1, Line 38: /* Upper word is reserved and : Linux complains about 32 bit. */
Origins of the comment: https://review.coreboot.org/1691 […]
Looks like ICH7 uses 18 bits... ICH9 14... ACPI specifies 14 of the 16-bit minimum.
Can't remember what Linux complained about, ofc. But a quick look suggests:
/* * If a valid register (Address != 0) and the (default_length > 0) * (Not a GPE register), then check the width against the default. */
from `drivers/acpi/acpica/tbfadt.c:661`. The default is 16 bits.
So I guess while it is technically not wrong to set `len > 2`, the comment seems true.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42652 )
Change subject: sb/intel/i82801gx/fadt.c: Align with i82801ix ......................................................................
sb/intel/i82801gx/fadt.c: Align with i82801ix
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: I930de15a6746936fa4a8f6db280b5ac60176c836 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42652 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr --- M src/southbridge/intel/i82801gx/fadt.c 1 file changed, 18 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 7c35d44..dca4bb4 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -35,7 +35,8 @@ fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; @@ -53,7 +54,7 @@ fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->iapc_boot_arch = 0x03; + fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER @@ -61,68 +62,68 @@ if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
- fadt->reset_reg.space_id = 1; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06;
- fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0;
- fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0;
- fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0;
- fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0;
- fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0;
- fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0;
- fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0;
- fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; }