[XS] Change in coreboot[main]: soc/intel/common/block: Include register offsets for POWER_CTL

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84178?usp=email )

Change subject: soc/intel/common/block: Include register offsets for POWER_CTL
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soc/intel/common/block: Include register offsets for POWER_CTL

Details:
- Add (POWER_CTL) – Offset 0x1fc required bits.

Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Signed-off-by: Saurabh Mishra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Pratikkumar V Prajapati 
---
M src/soc/intel/common/block/include/intelblocks/msr.h
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  build bot (Jenkins): Verified
  Pratikkumar V Prajapati: Looks good to me, approved

diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 158cc9e..a030328 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -50,7 +50,10 @@
 #define  PRMRR_PHYS_MASK_VALID		(1 << 11)
 #define MSR_PRMRR_VALID_CONFIG		0x1fb
 #define MSR_POWER_CTL			0x1fc
+#define  ENABLE_BIDIR_PROCHOT		(1 << 0)
 #define  POWER_CTL_C1E_MASK		(1 << 1)
+#define  PWR_PERF_PLATFORM_OVR		(1 << 18)
+#define  VR_THERM_ALERT_DISABLE_LOCK	(1 << 23)
 #define MSR_PRMRR_BASE_0		0x2a0
 #define MSR_EVICT_CTL			0x2e0
 #define MSR_LT_CONTROL			0x2e7