New patch to review for coreboot: fff92ac tegra: Change how tegra124 and tegra include files from each other.
Isaac Christensen (isaac.christensen@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6659
-gerrit
commit fff92ac5d8649136e60b925fb3bd9a67fd25108b Author: Gabe Black gabeblack@google.com Date: Sun Oct 6 06:13:24 2013 -0700
tegra: Change how tegra124 and tegra include files from each other.
A problem with including the tegra124 directory directly in the include path is that it makes all headers in that directory first level headers available everywhere including places that have nothing to do with the SOC, even headers which were only intended for local use by tegra124 code. This change modifies things a bit to be more like the way the arch headers are chosen. In the tegra124 directory, there's an include directory which has an soc subdirectory in it. That include directory is added to the include path, making it possible to have headers private to the tegra124. When files specific to whatever tegra is being built for are needed, you can include <soc/foo.h> and get the version specific to that particular soc.
Also, the soc.h header file was overhauled to use enums instead of defines, to consistently name things as far as their prefix (the less cryptic TEGRA instead of NV_PA) and suffixes like "BASE", and to get rid of values which were specific to U-Boot which we don't need. Since the only thing in the file were address constants, I also renamed the file addressmap.h. It would be included as:
<soc/addressmap.h>
which I think is easy to remember, does what you'd think it does from the name, and won't conflict with other header files just minding their own business in some other directory.
Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55 Signed-off-by: Gabe Black gabeblack@google.com Reviewed-on: https://chromium-review.googlesource.com/172080 Reviewed-by: Julius Werner jwerner@chromium.org Reviewed-by: Ronald Minnich rminnich@chromium.org Tested-by: Gabe Black gabeblack@chromium.org Commit-Queue: Gabe Black gabeblack@chromium.org (cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858) Signed-off-by: Isaac Christensen isaac.christensen@se-eng.com --- src/soc/nvidia/tegra124/Makefile.inc | 2 +- src/soc/nvidia/tegra124/clock.c | 9 ++-- src/soc/nvidia/tegra124/include/soc/addressmap.h | 60 ++++++++++++++++++++++ src/soc/nvidia/tegra124/soc.h | 64 ------------------------ 4 files changed, 66 insertions(+), 69 deletions(-)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 0037a69..b8541fb 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -13,7 +13,7 @@ ramstage-y += cbfs.c ramstage-y += monotonic_timer.c ramstage-y += timer.c
-INCLUDES += -Isrc/soc/nvidia/tegra124 -Isrc/soc/nvidia +INCLUDES += -Isrc/soc/nvidia/tegra124/include/
# We want to grab the bootblock right before it goes into the image and wrap # it inside a BCT, but ideally we would do that without making special, one diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 691a6ee..af01b56 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -16,11 +16,12 @@
#include <delay.h> #include <arch/io.h> -#include <soc.h> -#include <clk_rst.h> -#include <clock.h> +#include <soc/addressmap.h>
-static struct clk_rst_ctlr *clk_rst = (void *)NV_PA_CLK_RST_BASE; +#include "clk_rst.h" +#include "clock.h" + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; /* * On poweron, AVP clock source (also called system clock) is set to PLLP_out0 * with frequency set at 1MHz. Before initializing PLLP, we need to move the diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h new file mode 100644 index 0000000..edacf15 --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2013 Google Inc. + * + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ +#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ + +enum { + TEGRA_SRAM_BASE = 0x40000000, + TEGRA_SRAM_SIZE = 0x20000 +}; + +enum { + TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_PG_UP_BASE = 0x60000000, + TEGRA_TMRUS_BASE = 0x60005010, + TEGRA_CLK_RST_BASE = 0x60006000, + TEGRA_FLOW_BASE = 0x60007000, + TEGRA_GPIO_BASE = 0x6000D000, + TEGRA_EVP_BASE = 0x6000F000, + TEGRA_APB_MISC_BASE = 0x70000000, + TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, + TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, + TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, + TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, + TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300, + TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400, + TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000, + TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380, + TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400, + TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600, + TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800, + TEGRA_SLINK4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, + TEGRA_SLINK5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, + TEGRA_SLINK6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, + TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000, + TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, + TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400, + TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, + TEGRA_CSITE_BASE = 0x70040000, + TEGRA_USB_ADDR_MASK = 0xFFFFC000, +}; + +#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra124/soc.h b/src/soc/nvidia/tegra124/soc.h deleted file mode 100644 index 7a164b0..0000000 --- a/src/soc/nvidia/tegra124/soc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2013 Google Inc. - * - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see http://www.gnu.org/licenses/. - */ - -#ifndef _TEGRA124_SOC_H - -/* AP base physical address of internal SRAM */ -#define NV_PA_BASE_SRAM 0x40000000 -#define NV_PA_BASE_SRAM_SIZE 0x20000 - -/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ -#define NV_WB_RUN_ADDRESS 0x40020000 - -#define NV_PA_ARM_PERIPHBASE 0x50040000 -#define NV_PA_PG_UP_BASE 0x60000000 -#define NV_PA_TMRUS_BASE 0x60005010 -#define NV_PA_CLK_RST_BASE 0x60006000 -#define NV_PA_FLOW_BASE 0x60007000 -#define NV_PA_GPIO_BASE 0x6000D000 -#define NV_PA_EVP_BASE 0x6000F000 -#define NV_PA_APB_MISC_BASE 0x70000000 -#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) -#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) -#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) -#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) -#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) -#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) -#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) -#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) -#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) -#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) -#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) -#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) -#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) -#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) -#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) -#define NV_PA_CSITE_BASE 0x70040000 -#define TEGRA_USB_ADDR_MASK 0xFFFFC000 - -#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE - -#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ - -#endif /* _TEGRA124_SOC_H_ */
-
Isaac Christensen