Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 )

Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices
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Patch Set 20: Code-Review-2

(1 comment)

southbridge/intel/common has code to do exactly this, besides that you may want to avoid generating the the legacy PIC entries. You just need implement the function to map int pin to int line.

https://review.coreboot.org/c/coreboot/+/34089/20/src/soc/intel/common/block... 
File src/soc/intel/common/block/itss/irq.c:

https://review.coreboot.org/c/coreboot/+/34089/20/src/soc/intel/common/block... 
PS20, Line 35: static void create_irq_entry(const struct device *dev,
             : 		struct dev_irq *irq_entry)
             : {
             : 	static int slot;
             : 	/* PIRx mapped from IRQ# 16:23 starting from PIRQA */
             : 	static int int_line = PIRQA_APIC_IRQ;
             : 	static int int_lpss = PIRQA_APIC_IRQ;
             : 
             : 	irq_entry->slot = PCI_SLOT(dev->path.pci.devfn);
             : 	irq_entry->func = PCI_FUNC(dev->path.pci.devfn);
             : 
             : 	if (!is_dev_lpss(dev)) {
             : 		/* Devices that have shared IRQ routing */
             : 		if (slot != PCI_SLOT(dev->path.pci.devfn))
             : 			int_line = PIRQA_APIC_IRQ;
             : 		irq_entry->int_line = int_line++;
             : 	} else {
             : 		/* LPSS controllers needs unique IRQ assignments */
             : 		irq_entry->int_line = int_lpss++;
             : 	}
             : 
             : 	/* Assign INTA, INTB, INTC, INTD */
             : 	irq_entry->int_pin = (irq_entry->int_line % 4) + 1;
             : 
             : 	/* only interrupt 16-23 can be shared */
             : 	if (int_line > 23)
             : 		int_line = PIRQA_APIC_IRQ;
             : 
             : 	/*
             : 	 * if lpss irq# extends beyond irq#23, it will conflict with gpio irqs
             : 	 * (23- 119). The conflicting gpios should not be configured to use irq
             : 	 * trigger via IOAPIC then.
             : 	 */
             : 	if (int_lpss > 23)
             : 		printk(BIOS_ERR, "LPSS controller D: 0x%x F: 0x%x uses irq %d"
             : 				", conflicts with gpio mapped to irq %d\n",
             : 				irq_entry->slot, irq_entry->func, int_lpss,
             : 				int_lpss);
             : 
             : 	slot = PCI_SLOT(dev->path.pci.devfn);
             : }
This can be implemented as the in intel_common_map_pirq() in southbridge/intel/common/acpi_pirq_gen.c