Patch set updated for coreboot: nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13148

-gerrit

commit b6793ee3fac1dc1367e0c207877218473b6a78c5
Author: Timothy Pearson <[e-mail]>
Date:   Tue Nov 24 14:11:52 2015 -0600

    nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
    
    Certain registered DIMMs failed training due to an error
    likely introduced during historical rebase.  Ensure that
    the SubMemclkRegDly bit is set according to BKDG
    recommendations on Family 15 processors.
    
    Change-Id: I24c95265dada9eabf4df280b6f2b4a1eb9cecaf1
    Signed-off-by: Timothy Pearson <[e-mail]>
---
 src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index cf13b40..fc62afb 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -66,6 +66,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
 		misc2 |= ((cs_mux_67 & 0x1) << 27);
 		misc2 &= ~(0x1 << 26);		/* CsMux45 = cs_mux_45 */
 		misc2 |= ((cs_mux_45 & 0x1) << 26);
+
+		if (pDCTstat->Status & (1 << SB_Registered))
+			misc2 |= 1 << SubMemclkRegDly;
 	} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
 		if (pDCTstat->Status & (1 << SB_Registered)) {
 			misc2 |= 1 << SubMemclkRegDly;