Change in coreboot[master]: address of riscv register is incorrect

[Anonymous Coward (Code Review)]

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20043

Change subject: address of riscv register is incorrect
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address of riscv register is incorrect

I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception.
This instruction is [csrwi 0x320,7].
Through this I found the register address wrong

Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a
signed-off-by: wxjstz
Signed-off-by: wxjstz 
---
M src/arch/riscv/virtual_memory.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20043/1

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 2c440d2..9ab7548 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -316,6 +316,6 @@
    // Until we trust our toolchain use the hardcoded constants.
    // These were in flux and people who get the older toolchain
    // will have difficult-to-debug failures.
-	write_csr(/*mucounteren*/0x320, 7);
-	write_csr(/*mscounteren*/0x321, 7);
+	write_csr(/*mcounteren*/0x306, 7);
+	write_csr(/*scounteren*/0x106, 7);
 }