[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers

[David Hendricks (Code Review)]

Attention is currently required from: Angel Pons, Annie Chen, Arthur Heymans, Felix Singer, Hung-Wei Chen, Jonathan Zhang, Lean Sheng Tan, Paul Menzel.

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75598?usp=email )

Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
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Patch Set 8:

(4 comments)

File src/mainboard/inventec/transformers/bootblock.c:

https://review.coreboot.org/c/coreboot/+/75598/comment/21e1879c_c328ffc1 :
PS5, Line 23: 	 * For ArcherCity CRB, only SUART1 is used.
> This seems copy-pasted.

Yeah, parts will be factored out (same with CB:75722).

File src/mainboard/inventec/transformers/romstage.c:

https://review.coreboot.org/c/coreboot/+/75598/comment/61cd28f1_18e4d14f :
PS5, Line 102: 	    selftest result first */
> Please align the line correctly.

Done

https://review.coreboot.org/c/coreboot/+/75598/comment/587e0557_bfab73cc :
PS5, Line 118: /* Enable - Portions of memory reference code will be skipped */
             : 	/* when possible to increase boot speed on warm boots.*/
             : 	/* Disable - Disables this feature. */
             : 	/* Auto - Sets it to the MRC default setting. */
> Please use the multi-line commenting style listed in the coding style.

Done

https://review.coreboot.org/c/coreboot/+/75598/comment/b94ec765_46eabf7a :
PS5, Line 142: 	/* Disable FSP memory train results*/
> Please add a space at the end.

Done