Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registe...

[Subrata Banik (Code Review)]

Hello dhaval v sharma, Balaji Manigandan, build bot (Jenkins), Lijian Zhao,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/21235

to look at the new patch set (#6).

Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP]
......................................................................

soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP]

This patch ensures that entire system memory calculation is done
based on host bridge registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot cannonlake RVP successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
6. Enable C6 DRAM with PRMRR size 0MB and boot to OS.

Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/include/soc/iomap.h
M src/soc/intel/cannonlake/include/soc/systemagent.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/romstage/romstage.c
5 files changed, 142 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/21235/6