Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath.
Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50996

to look at the new patch set (#4).

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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mb/adlrvp: Fix DDR5 Boot issue

Currently, DDR5 boot is broken due to reading of spd data
via SMBus through coreboot. This implementation requires study
of spd5 architecture and is currently Work In Progress.
Switching to the older implemention of booting DDR5 by passing
DIMM slave address to FSP through this CL.

BUG=b:180458099
TEST=Boot DDR5 to kernel

Signed-off-by: Meera Ravindranath 
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/4