Change in coreboot[master]: md/SuperIO: Change DUMMY_DEV to SUPERIO_DEV for global control device - coreboot-gerrit

26 Apr 2018

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25852
Change subject: md/SuperIO: Change DUMMY_DEV to SUPERIO_DEV for global control device
......................................................................
md/SuperIO: Change DUMMY_DEV to SUPERIO_DEV for global control device
Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr
---
M src/mainboard/google/beltino/onboard.h
M src/mainboard/google/beltino/romstage.c
M src/mainboard/google/jecht/onboard.h
M src/mainboard/google/jecht/romstage.c
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/samsung/stumpy/smihandler.c
M src/mainboard/supermicro/h8dme/romstage.c
M src/mainboard/supermicro/h8dmr/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/via/epia-m700/romstage.c
12 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/25852/1

diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h
index 29da766..2e07309 100644
--- a/src/mainboard/google/beltino/onboard.h
+++ b/src/mainboard/google/beltino/onboard.h
@@ -31,7 +31,7 @@
 #define IT8772F_BASE 0x2e
 #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)
 #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
-#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0)
+#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0)
#ifndef __ACPI__
 void lan_init(void);
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 2ddb9b1..b0468f5 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -137,7 +137,7 @@
/* Early SuperIO setup */
    ite_kill_watchdog(IT8772F_GPIO_DEV);
-	it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
+	it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
    pch_enable_lpc();
    ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h
index a911fe6..d92aa16 100644
--- a/src/mainboard/google/jecht/onboard.h
+++ b/src/mainboard/google/jecht/onboard.h
@@ -50,6 +50,6 @@
 #define IT8772F_BASE 0x2e
 #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)
 #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
-#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0)
+#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0)
#endif
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
index 6203a1e..c3a5720 100644
--- a/src/mainboard/google/jecht/romstage.c
+++ b/src/mainboard/google/jecht/romstage.c
@@ -54,7 +54,7 @@
 void mainboard_pre_console_init(void)
 {
    /* Early SuperIO setup */
-	it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
+	it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
    ite_kill_watchdog(IT8772F_GPIO_DEV);
    ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 1b8bb95..dd384ac 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -37,7 +37,7 @@
 #include <southbridge/intel/i82801gx/i82801gx.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-#define DUMMY_DEV PNP_DEV(0x4e, 0)
+#define SUPERIO_DEV PNP_DEV(0x4e, 0)
static void ich7_enable_lpc(void)
 {
@@ -63,7 +63,7 @@
 {
    pnp_devfn_t dev;
-	dev = DUMMY_DEV;
+	dev = SUPERIO_DEV;
    pnp_enter_conf_state(dev);
pnp_write_config(dev, 0x24, 0xc4); // PNPCVS
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 1b5d2ae..0da658c 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -52,7 +52,7 @@
 #endif
 #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
@@ -123,17 +123,17 @@
     * GPIO10 as USBPWRON12#
     * GPIO12 as USBPWRON13#
     */
-	it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05);
+	it8772f_gpio_setup(SUPERIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05);
/*
     * GPIO22 as wake SCI#
     */
-	it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04);
+	it8772f_gpio_setup(SUPERIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04);
/*
     * GPIO32 as EXTSMI#
     */
-	it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04);
+	it8772f_gpio_setup(SUPERIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04);
/*
     * GPIO45 as LED_POWER#
@@ -147,8 +147,8 @@
     * GPIO51 as USBPWRON8#
     * GPIO52 as USBPWRON1#
     */
-	it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06);
-	it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);
+	it8772f_gpio_setup(SUPERIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06);
+	it8772f_gpio_setup(SUPERIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);
 }
void mainboard_fill_pei_data(struct pei_data *pei_data)
@@ -258,7 +258,7 @@
    setup_sio_gpios();
/* Early SuperIO setup */
-	it8772f_ac_resume_southbridge(DUMMY_DEV);
+	it8772f_ac_resume_southbridge(SUPERIO_DEV);
    ite_kill_watchdog(GPIO_DEV);
    ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 }
diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c
index 00148f2..ad27bce 100644
--- a/src/mainboard/samsung/stumpy/smihandler.c
+++ b/src/mainboard/samsung/stumpy/smihandler.c
@@ -25,7 +25,7 @@
/* Include for SIO helper functions */
 #include <superio/ite/it8772f/it8772f.h>
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
/*
  * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
@@ -36,14 +36,14 @@
    switch (slp_typ) {
    case ACPI_S3:
    case ACPI_S4:
-		it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */,
+		it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */,
    		(0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */,
    		(0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */
    		SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
    	break;
case ACPI_S5:
-		it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1 << 5) /* select */,
+		it8772f_gpio_led(SUPERIO_DEV, 4 /* set */, (0x1 << 5) /* select */,
    		0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,
    		(0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */,
    		SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 9deb940..13cb038 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -36,7 +36,7 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
unsigned get_sbdn(unsigned bus);
@@ -140,7 +140,7 @@
    if (bist == 0)
    	bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	winbond_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(SUPERIO_DEV);
    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 9da1ab5..a766f01 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -39,7 +39,7 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
unsigned get_sbdn(unsigned bus);
@@ -120,7 +120,7 @@
    if (bist == 0)
    	bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	winbond_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(SUPERIO_DEV);
    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index fa22952..c360389 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -50,7 +50,7 @@
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
void activate_spd_rom(const struct mem_controller *ctrl);
 int spd_read_byte(unsigned device, unsigned address);
@@ -130,7 +130,7 @@
post_code(0x32);
-	winbond_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(SUPERIO_DEV);
    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 8c693a8..723a665 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -49,7 +49,7 @@
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
#define SMBUS_SWITCH1 0x70
 #define SMBUS_SWITCH2 0x72
@@ -195,7 +195,7 @@
post_code(0x32);
-	winbond_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(SUPERIO_DEV);
    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index faf87c7..0aeec7a 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -41,7 +41,7 @@
 #include <superio/winbond/w83697hf/w83697hf.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
/*
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
@@ -378,7 +378,7 @@
     */
    pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
    /* EmbedComInit(); */
-	winbond_set_clksel_48(DUMMY_DEV);
+	winbond_set_clksel_48(SUPERIO_DEV);
    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
    /* enable_vx800_serial(); */
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61
Gerrit-Change-Number: 25852
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS ehaouas@noos.fr



    