Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 7:

(2 comments)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63293/comment/5b532eed_277b2aed 
PS7, Line 578: 	 * Add Workaround to disable PCH USB2 Phy power gating as per Intel TA# 723158 to
             : 	 * prevent possible display flicker issue.
             : 	 * Enable or Disable PCH USB2 Phy power gating.
             : 	 * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
> unrelated to the TA ?

I said in general that usb2_phy_sus_pg_enable UPD can be disabled different purpose like debugging. As we all know there will be power impact if the UPD is not enabled. For now, we are disabling the UPD due to the TA.

https://review.coreboot.org/c/coreboot/+/63293/comment/62d3cfbe_02feb4f3 
PS7, Line 582: 	 *
> nit; extra blank line

Ack