Attention is currently required from: Jérémy Compostella.
Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email )
Change subject: soc/intel/common/block/cpu: Use the effective way size for NEM+ ......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/83946/comment/f5c44d34_71cd06ff?usp... : PS4, Line 498: INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE As I learned from the Intel cache team during another hang issue in Ovis with 18MB of cache, when we have a cache size that is not a power of two, we can still use the entire cache lines to get the cache read benefit (and not write hence, WB configuration of NEM memory breaks there). However, those extra lines (outside of the power of two) will not be mapped to physical memory during tear down. As a result, any data that we rely on that is greater than the power of two range will cause a hang
It appears that you are attempting to limit the cache size itself to a power of two when the SoC cache size is not aligned with a power of two. For example, if the cache size is 18MB, only 16MB will be available for use.