[M] Change in coreboot[master]: soc/amd/morgana: Add 32M support

[Bao Zheng (Code Review)]

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Felix Held.

Hello Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/69150

to look at the new patch set (#2).

Change subject: soc/amd/morgana: Add 32M support
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soc/amd/morgana: Add 32M support

The 32M has to be divided into 2 16M parts, top and bottom. We can
only map one part at one time. By default, the bottom 16M is mapped to
0xFF000000-0xFFFFFFFF. By this default setting, the address in the
image is not the actual phyical address. So we need to convert the
address, or map the upper 16M instead (the easier way UEFI BIOS
does). So we push all the modules with running code, like romstage,
ramstage, even the fmap table, to upper 16M. For the bootblock part,
which is loaded by bootloader, it is unchanged as a tiny relocatable
image in bottom 16M in amdfw.rom.

Since the amdfw.rom is not in CFBS, we put it in fmap.

We put only EC FWs and PSP FWs in the botttom, where the PSP can
load.

If coreboot need to access bottom 16M, which in fact doesn't seem to
be necessary, can be implemented by SMN command.

The bit 14 of soft fuse decides which (top or bottom) 16M is mapped to
4G-16M.

BUG=b:255374782

Change-Id: Ia0b5a75f828033b29c378bed9a939b23d7f19140
Signed-off-by: Zheng Bao 
---
M src/mainboard/amd/birman/Kconfig
M src/mainboard/amd/birman/board.fmd
M src/mainboard/amd/birman/chromeos.fmd
M src/soc/amd/morgana/Kconfig
M src/soc/amd/morgana/Makefile.inc
5 files changed, 53 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/69150/2