Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49833 )
Change subject: bayhub bh720: Factor out common HS200 init code ......................................................................
bayhub bh720: Factor out common HS200 init code
Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy.
Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub/bh720.h M src/drivers/generic/bayhub/chip.h M src/mainboard/google/kahlee/variants/baseboard/mainboard.c M src/mainboard/google/sarien/Makefile.inc D src/mainboard/google/sarien/mainboard.c 6 files changed, 49 insertions(+), 109 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved
diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 2438664..40788cd 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -4,6 +4,7 @@
#include <console/console.h> #include <device/device.h> +#include <device/mmio.h> #include <device/path.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -11,8 +12,50 @@ #include "chip.h" #include "bh720.h"
-__attribute__((weak)) void board_bh720(struct device *dev) +static void bh720_program_hs200_mode(struct device *dev) { + u32 sdbar; + u32 bh720_pcr_data; + + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); }
static void bh720_init(struct device *dev) @@ -43,7 +86,8 @@ pci_read_config32(dev, BH720_LINK_CTRL)); }
- board_bh720(dev); + if (config && !config->disable_hs200_mode) + bh720_program_hs200_mode(dev);
if (config && config->vih_tuning_value) { /* Tune VIH */ diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index d8c3196..cc5fbea 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -39,5 +39,3 @@ BH720_PCR_CSR = 0x3e4, BH720_PCR_CSR_EMMC_MODE_SEL = BIT(22), }; - -void board_bh720(struct device *dev); diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h index f898378..77b7512 100644 --- a/src/drivers/generic/bayhub/chip.h +++ b/src/drivers/generic/bayhub/chip.h @@ -9,6 +9,9 @@ /* 1 to enable power-saving mode, 0 to disable */ int power_saving;
+ /* When set, disables programming HS200 mode */ + bool disable_hs200_mode; + /* CLK and DAT tuning values */ uint8_t vih_tuning_value; }; diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 860190a..7893449 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -7,9 +7,6 @@ #include <gpio.h> #include <smbios.h> #include <variant/gpio.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <drivers/generic/bayhub/bh720.h>
uint32_t sku_id(void) { @@ -32,52 +29,6 @@ gpio_set(GPIO_133, 0); }
-void board_bh720(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); - - /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - bh720_pcr_data &= 0x0000FFFF; - bh720_pcr_data |= 0x2510 << 16; - write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); - - /* Use PLL Base clock PCR 0x3E4[22] = 1 */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_CSR); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_CSR); - - /* Disable Memory Access */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); -} - const char *smbios_mainboard_manufacturer(void) { static char oem_bin_data[11]; diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index e7c23b1..12e08be 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -2,7 +2,6 @@
bootblock-y += bootblock.c
-ramstage-y += mainboard.c ramstage-y += ramstage.c ramstage-y += sku.c
diff --git a/src/mainboard/google/sarien/mainboard.c b/src/mainboard/google/sarien/mainboard.c deleted file mode 100644 index 5399e6c..0000000 --- a/src/mainboard/google/sarien/mainboard.c +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <drivers/generic/bayhub/bh720.h> -#include <string.h> - -void board_bh720(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - printk(BIOS_DEBUG, "mainboard: %s init\n", __func__); - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); - - /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - bh720_pcr_data &= 0x0000FFFF; - bh720_pcr_data |= 0x2510 << 16; - write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); - - /* Use PLL Base clock PCR 0x3E4[22] = 1 */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_CSR); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_CSR); - - /* Disable Memory Access */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); -}
-
Patrick Georgi (Code Review)