[XS] Change in coreboot[main]: soc/amd/cezanne: Give PSP verstage 4K more space

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83564?usp=email )

Change subject: soc/amd/cezanne: Give PSP verstage 4K more space
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soc/amd/cezanne: Give PSP verstage 4K more space

To allow CMOS initialization in verstage, the current reserved size 108K
(PSP_SRAM_SIZE - PSP_VERSTAGE_STACK_SIZE = 148K - 40K) is not enough.
Preserve more space for verstage by reducing the stack size by 4K.

Change-Id: I9f53a45d67782d3e425f423d0715a45482b2edea
Signed-off-by: Yu-Ping Wu 
---
M src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/83564/1

diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
index 569d6e1..ab11448 100644
--- a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
+++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
@@ -17,7 +17,7 @@
  * and make the size a multiple of 4k
  */

-#define PSP_VERSTAGE_STACK_START	0x41000
-#define PSP_VERSTAGE_STACK_SIZE		(40K)
+#define PSP_VERSTAGE_STACK_START	0x42000
+#define PSP_VERSTAGE_STACK_SIZE		(36K)

#endif  /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */