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Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Sugnan Prabhu S, Subrata Banik, Bernardo Perez Priego, Ronak Kanabar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52270
to look at the new patch set (#10).
Change subject: mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
......................................................................
mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.
Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com
---
M src/mainboard/intel/adlrvp/early_gpio.c
1 file changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52270/10
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Gerrit-Change-Number: 52270
Gerrit-PatchSet: 10
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