Change in coreboot[master]: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet...
Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44520 )
Change subject: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche ......................................................................
mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche
Add LPDDR4x DRAM index#6 MT53E2G32D4NQ-046 8GB
BUG=b:159301679 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. MT53E2G32D4NQ-046 8GB M/B boot successfully 3. check DRAM size: 8GB
Change-Id: I16449591ec576b1c613a5dad511bafac2bb46f04 Signed-off-by: Kevin Chiu kevin.chiu@quantatw.com --- M src/mainboard/google/kukui/sdram_configs.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/44520/1
diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 95306c7..54f0ef9 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -28,6 +28,7 @@ [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", };
static struct sdram_params params;
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44520 )
Change subject: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche ......................................................................
Patch Set 1:
(1 comment)
why
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... File src/mainboard/google/kukui/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... PS1, Line 31: 0x16 then what is #5? why skip one?
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44520 )
Change subject: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... File src/mainboard/google/kukui/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... PS1, Line 31: 0x16
then what is #5? why skip one?
Hi Hung-Te, originally H/W reserve ID#5 for MT53E1G32D2NP-046 WT:A but due to its single rank and SOC can't support it, that's why ID#5 is skipped.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44520 )
Change subject: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... File src/mainboard/google/kukui/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... PS1, Line 31: 0x16
Hi Hung-Te, […]
Hi Kevin
If no boards have been manufactured with that ID and we're not going to use that module in future (given SOC can't support it), I see no reason we want to keep #5 unused. Please check with Google HW team to see if they agree to re-allocate. Please remember we have only 12 IDs, unless if you are going to have #5 defined for something else very soon.
Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44520 )
Change subject: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... File src/mainboard/google/kukui/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... PS1, Line 31: 0x16
Hi Kevin […]
Hi Hung-Te, per checked with H/W, ID5 will be used at next phase but now will keep it empty due to unsupported DRAM was chosen. so could we merge this one for micron 8GB support to test? thanks.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44520 )
Change subject: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... File src/mainboard/google/kukui/sdram_configs.c:
https://review.coreboot.org/c/coreboot/+/44520/1/src/mainboard/google/kukui/... PS1, Line 31: 0x16
Hi Hung-Te, […]
Sure.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44520 )
Change subject: mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche ......................................................................
mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/esche
Add LPDDR4x DRAM index#6 MT53E2G32D4NQ-046 8GB
BUG=b:159301679 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. MT53E2G32D4NQ-046 8GB M/B boot successfully 3. check DRAM size: 8GB
Change-Id: I16449591ec576b1c613a5dad511bafac2bb46f04 Signed-off-by: Kevin Chiu kevin.chiu@quantatw.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44520 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/mainboard/google/kukui/sdram_configs.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 95306c7..54f0ef9 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -28,6 +28,7 @@ [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", };
static struct sdram_params params;
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Hung-Te Lin (Code Review) -
Kevin Chiu (Code Review)
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Patrick Georgi (Code Review)