Attention is currently required from: Kapil Porwal, Nick Vaccaro, Nico Huber, Subrata Banik.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80500?usp=email )
Change subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80500/comment/89f45c7a_a06299f3 :
PS2, Line 13:
Did you notice any difference in behavior?
Not particularly visible, but what FSP does with these is the proper configuration of the sideband use BSSB_LSx pins for the enabled Type-C ports, which might be important for some initialization of DCI debug and Tyep-C SubSystem overall.
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