Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46949 )
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c 8 files changed, 25 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46949/1
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 09cab17..481a593 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -168,12 +168,19 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void);
+void set_max_freq(void); + /* CPU identification */ static inline u32 cpu_family_model(void) { return cpuid_eax(1) & 0x0fff0ff0; }
+static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + static inline int haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP) || CONFIG(SOC_INTEL_BROADWELL); diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/soc/intel/broadwell/cpu/romstage.c index 959a123..f4b913f 100644 --- a/src/soc/intel/broadwell/cpu/romstage.c +++ b/src/soc/intel/broadwell/cpu/romstage.c @@ -3,8 +3,7 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <soc/intel/broadwell/romstage.h> -#include "haswell.h" +#include <cpu/intel/haswell/haswell.h>
void set_max_freq(void) { diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index a448237..8370167 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <bootmode.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -20,7 +21,6 @@ #include <security/vboot/vbnv.h> #include <types.h>
-#include "cpu/haswell.h" #include "haswell.h"
#define GT_RETRY 1000 @@ -524,7 +524,7 @@ reg_script_run_on_dev(dev, broadwell_early_init_script);
/* Set GFXPAUSE based on stepping */ - if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) && + if (cpu_stepping() <= (CPUID_BROADWELL_ULT_E0 & 0xf) && systemagent_revision() <= 9) { gtt_write(0xa000, 0x300ff); } else { diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 73c6e83..33293a4 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -10,8 +10,8 @@ #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/intel/broadwell/memmap.h> +#include <cpu/intel/haswell/haswell.h>
-#include "cpu/haswell.h" #include "haswell.h" #include "ramstage.h"
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index f43fa78..8bf7d3d 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -11,7 +11,7 @@ #include <soc/intel/broadwell/pch/chip.h> #include <delay.h>
-#include "../cpu/haswell.h" +#include <cpu/intel/haswell/haswell.h> #include "gpio.h" #include "iobp.h" #include "pch.h" diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/xhci.c index 50c69d2..5679ff3 100644 --- a/src/soc/intel/broadwell/pch/xhci.c +++ b/src/soc/intel/broadwell/pch/xhci.c @@ -8,8 +8,8 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/cpu.h> +#include <cpu/intel/haswell/haswell.h>
-#include "../cpu/haswell.h" #include "xhci.h"
#ifdef __SIMPLE_DEVICE__ diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index b649ebb..ad5a109 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -7,25 +7,26 @@ #include <string.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> +#include <cpu/intel/haswell/haswell.h> #include <soc/intel/broadwell/romstage.h>
#include <soc/intel/broadwell/haswell.h> -#include "cpu/haswell.h" #include "pch/pch.h"
+/* FIXME: Needs an update */ static struct { u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_HASWELL_A0, "Haswell A0" }, - { CPUID_HASWELL_B0, "Haswell B0" }, - { CPUID_HASWELL_C0, "Haswell C0" }, - { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, - { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" }, - { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, - { CPUID_BROADWELL_C0, "Broadwell C0" }, - { CPUID_BROADWELL_D0, "Broadwell D0" }, - { CPUID_BROADWELL_E0, "Broadwell E0 or F0" }, + { CPUID_HASWELL_A0, "Haswell A0" }, + { CPUID_HASWELL_B0, "Haswell B0" }, + { CPUID_HASWELL_C0, "Haswell C0" }, + { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, + { CPUID_HASWELL_ULT_C0, "Haswell ULT C0 or D0" }, + { CPUID_CRYSTALWELL_C0, "Haswell Perf Halo" }, + { CPUID_BROADWELL_ULT_C0, "Broadwell C0" }, + { CPUID_BROADWELL_ULT_D0, "Broadwell D0" }, + { CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" }, };
static struct { diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 165d649..f9242fd 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <arch/romstage.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <elog.h> #include <romstage_handoff.h> #include <soc/intel/broadwell/pch/pm.h> @@ -10,7 +11,6 @@ #include <stdint.h> #include <timestamp.h>
-#include "cpu/haswell.h" #include "haswell.h" #include "pei_data.h" #include "pch/gpio.h"
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46949
to look at the new patch set (#5).
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c 8 files changed, 25 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46949/5
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46949
to look at the new patch set (#7).
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c 10 files changed, 26 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46949/7
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46949
to look at the new patch set (#8).
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c 10 files changed, 26 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46949/8
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46949
to look at the new patch set (#12).
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c 11 files changed, 26 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46949/12
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46949 )
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
Patch Set 15: Code-Review+1
(1 comment)
File src/cpu/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/46949/comment/8e946619_f0ff3a3b PS15, Line 173: /* CPU identification */ : static inline u32 cpu_family_model(void) : { : return cpuid_eax(1) & 0x0fff0ff0; : } : : static inline u32 cpu_stepping(void) : { : return cpuid_eax(1) & 0xf; : } Not a fan of these non-haswell specific things here.
Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46949 )
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
Patch Set 15:
(1 comment)
File src/cpu/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/46949/comment/74ba2773_f5dcd776 PS15, Line 173: /* CPU identification */ : static inline u32 cpu_family_model(void) : { : return cpuid_eax(1) & 0x0fff0ff0; : } : : static inline u32 cpu_stepping(void) : { : return cpuid_eax(1) & 0xf; : }
Not a fan of these non-haswell specific things here.
I would move them to cpu/intel/common but these may not work for model F CPUs
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46949 )
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
Patch Set 15: Code-Review+2
(1 comment)
File src/cpu/intel/haswell/haswell.h:
https://review.coreboot.org/c/coreboot/+/46949/comment/0411e908_ec6b6cc1 PS15, Line 173: /* CPU identification */ : static inline u32 cpu_family_model(void) : { : return cpuid_eax(1) & 0x0fff0ff0; : } : : static inline u32 cpu_stepping(void) : { : return cpuid_eax(1) & 0xf; : }
I would move them to cpu/intel/common but these may not work for model F CPUs
Can we leverage get_fms into some static inlines to get model, family and stepping? Let's however not delay this patchtrain because of this.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46949 )
Change subject: soc/intel/broadwell: Use Haswell CPU headers ......................................................................
soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46949 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/haswell.h M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/romstage.c M src/soc/intel/broadwell/gma.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/xhci.c M src/soc/intel/broadwell/report_platform.c M src/soc/intel/broadwell/romstage.c 11 files changed, 26 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index e45acd5..133a129 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -168,12 +168,19 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void);
+void set_max_freq(void); + /* CPU identification */ static inline u32 cpu_family_model(void) { return cpuid_eax(1) & 0x0fff0ff0; }
+static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + static inline int haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index dbaade6..5df44fb 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -6,6 +6,7 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cbmem.h> +#include <cpu/intel/haswell/haswell.h> #include <device/pci_ops.h> #include <cpu/x86/smm.h> #include <console/console.h> @@ -15,10 +16,8 @@ #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/soc/intel/broadwell/cpu/romstage.c index c9f70a8..3b11e93 100644 --- a/src/soc/intel/broadwell/cpu/romstage.c +++ b/src/soc/intel/broadwell/cpu/romstage.c @@ -2,10 +2,8 @@
#include <arch/cpu.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/msr.h> -#include <soc/romstage.h>
void set_max_freq(void) { diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index bbb6678..6556dd4 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -6,6 +6,7 @@ #include <bootmode.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -16,7 +17,6 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> -#include <soc/cpu.h> #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -527,7 +527,7 @@ reg_script_run_on_dev(dev, broadwell_early_init_script);
/* Set GFXPAUSE based on stepping */ - if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) && + if (cpu_stepping() <= (CPUID_BROADWELL_ULT_E0 & 0xf) && systemagent_revision() <= 9) { gtt_write(0xa000, 0x300ff); } else { diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 721e23f..646ad0e 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -20,8 +20,6 @@ struct chipset_power_state *fill_power_state(void); void report_platform_info(void);
-void set_max_freq(void); - void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void); diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index e2b84b3..43fa081 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <acpi/acpi.h> #include <device/pci_ops.h> #include <stdint.h> @@ -10,7 +11,6 @@ #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 34f9c04..9a501c3 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -15,10 +15,8 @@ #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> #include <soc/acpi.h> -#include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index c98201e..b098dc2 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> @@ -14,7 +15,6 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> -#include <soc/cpu.h> #include <delay.h>
/* Low Power variant has 6 root ports. */ diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/xhci.c index baaf5ba..fd36fad 100644 --- a/src/soc/intel/broadwell/pch/xhci.c +++ b/src/soc/intel/broadwell/pch/xhci.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <cpu/intel/haswell/haswell.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -9,7 +10,6 @@ #include <device/pci_ops.h> #include <soc/ramstage.h> #include <soc/xhci.h> -#include <soc/cpu.h>
#ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index 4ed84d7..018ea24a 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -5,27 +5,28 @@ #include <console/console.h> #include <device/pci.h> #include <string.h> +#include <cpu/intel/haswell/haswell.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> -#include <soc/cpu.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/systemagent.h>
+/* FIXME: Needs an update */ static struct { u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_HASWELL_A0, "Haswell A0" }, - { CPUID_HASWELL_B0, "Haswell B0" }, - { CPUID_HASWELL_C0, "Haswell C0" }, - { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, - { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" }, - { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, - { CPUID_BROADWELL_C0, "Broadwell C0" }, - { CPUID_BROADWELL_D0, "Broadwell D0" }, - { CPUID_BROADWELL_E0, "Broadwell E0 or F0" }, + { CPUID_HASWELL_A0, "Haswell A0" }, + { CPUID_HASWELL_B0, "Haswell B0" }, + { CPUID_HASWELL_C0, "Haswell C0" }, + { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, + { CPUID_HASWELL_ULT_C0, "Haswell ULT C0 or D0" }, + { CPUID_CRYSTALWELL_C0, "Haswell Perf Halo" }, + { CPUID_BROADWELL_ULT_C0, "Broadwell C0" }, + { CPUID_BROADWELL_ULT_D0, "Broadwell D0" }, + { CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" }, };
static struct { diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 2e5db76..8e884d5 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <arch/romstage.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <elog.h> #include <romstage_handoff.h> #include <soc/gpio.h>
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)