[M] Change in coreboot[main]: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83393?usp=email )

Change subject: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility
......................................................................

soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility

This patch refactors the handling of CSE CBMEM IDs to enable platforms
to choose whether to perform CSE sync operations within coreboot or
defer it to the payload. This separation improves code organization,
ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks.

Now, platforms can select:
  * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot
  * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync

This change ensures mutually exclusive options, avoiding unnecessary
SPI flash size increases.

BUG=b:305898363
TEST=Builds and boots successfully:
    * google/rex0 with SOC_INTEL_CSE_LITE_SKU
    * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD

Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M payloads/libpayload/libc/coreboot.c
M src/soc/intel/common/block/cse/Makefile.mk
M src/soc/intel/common/block/cse/cse_lite.c
A src/soc/intel/common/block/cse/cse_sync_payload.c
4 files changed, 32 insertions(+), 25 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved

diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 7873426..1d914c5 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -262,12 +262,14 @@
    case CBMEM_ID_MEM_CHIP_INFO:
    	info->mem_chip_base = cbmem_entry->address;
    	break;
+#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)
    case CBMEM_ID_CSE_BP_INFO:
    	info->cse_bp_info = cbmem_entry->address;
    	break;
    case CBMEM_ID_CSE_INFO:
    	info->cse_info = cbmem_entry->address;
    	break;
+#endif
    default:
    	break;
    }
diff --git a/src/soc/intel/common/block/cse/Makefile.mk b/src/soc/intel/common/block/cse/Makefile.mk
index 653d674..d41d735 100644
--- a/src/soc/intel/common/block/cse/Makefile.mk
+++ b/src/soc/intel/common/block/cse/Makefile.mk
@@ -11,6 +11,8 @@
 ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c

+romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) += cse_sync_payload.c
+
 ifeq ($(CONFIG_STITCH_ME_BIN),y)

CSE_BP1_BIN := $(objcse)/cse_bp1.bin
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 4e3a446..6c4fed7 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1542,31 +1542,6 @@
    }
 }

-static void preram_create_cbmem_cse_info(int is_recovery)
-{
-	if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
-		return;
-
-	/*
-	 * CBMEM_ID_CSE_INFO will be used by the payload to -
-	 * 1. Avoid reading ISH firmware version on consecutive boots.
-	 * 2. Track state of PSR data during CSE downgrade operation.
-	 */
-	void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info));
-	if (!temp)
-		printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n");
-
-	/*
-	 * CBMEM_ID_CSE_BP_INFO will be used by the payload to avoid reading CSE
-	 * boot partition information on consecutive boots.
-	 */
-	temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp));
-	if (!temp)
-		printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n");
-}
-
-CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info);
-
 static void ramstage_cse_misc_ops(void *unused)
 {
    if (acpi_get_sleep_type() == ACPI_S3)
diff --git a/src/soc/intel/common/block/cse/cse_sync_payload.c b/src/soc/intel/common/block/cse/cse_sync_payload.c
new file mode 100644
index 0000000..5c816d1
--- /dev/null
+++ b/src/soc/intel/common/block/cse/cse_sync_payload.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/cse_lite.h>
+
+static void preram_create_cbmem_cse_info_for_payload(int is_recovery)
+{
+	/*
+	 * CBMEM_ID_CSE_INFO will be used by the payload to -
+	 * 1. Keep ISH firmware version on consecutive boots.
+	 * 2. Track state of PSR data during CSE downgrade operation.
+	 */
+	void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info));
+	if (!temp)
+		printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n");
+
+	/*
+	 * CBMEM_ID_CSE_BP_INFO will be used by the payload to keep CSE
+	 * boot partition information on consecutive boots.
+	 */
+	temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp));
+	if (!temp)
+		printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n");
+}
+
+CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info_for_payload);