Change in ...coreboot[master]: mb/google/{sarien,arcada} Fix SSD's power off sequence before going t...
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33410
Change subject: mb/google/{sarien,arcada} Fix SSD's power off sequence before going to S5 ......................................................................
mb/google/{sarien,arcada} Fix SSD's power off sequence before going to S5
BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin.
Change-Id: I5697350b2e23d4dfb0e546d95e089c91cd0070c6 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/smihandler.c M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 3 files changed, 14 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/33410/1
diff --git a/src/mainboard/google/sarien/smihandler.c b/src/mainboard/google/sarien/smihandler.c index 0efcaa9..aaa925c 100644 --- a/src/mainboard/google/sarien/smihandler.c +++ b/src/mainboard/google/sarien/smihandler.c @@ -13,10 +13,23 @@ * GNU General Public License for more details. */
+#include <arch/acpi.h> #include <cpu/x86/smm.h> +#include <delay.h> #include <ec/google/wilco/smm.h> +#include <gpio.h> #include <soc/smm.h> #include <variant/ec.h> +#include <variant/gpio.h> + +static void mainboard_gpio_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + gpio_set(GPIO_SSD_RESET, 0); + mdelay(1); + gpio_set(GPIO_SSD_POWER, 0); + } +}
void mainboard_smi_espi_handler(void) { @@ -25,6 +38,7 @@
void mainboard_smi_sleep(u8 slp_typ) { + mainboard_gpio_smi_sleep(slp_typ); wilco_ec_smi_sleep(slp_typ); }
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 4b05ba8..41121d2 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,8 +15,6 @@
#define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -#define SSD_EN GPP_H13 -#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -37,13 +35,6 @@
/* Clear touch screen pd pin to avoid leakage */ _SB.PCI0.CTXS (TS_PD) - - /* Clear SSD EN adn RST pin to avoid leakage */ - If (Arg0 == 5) { - _SB.PCI0.CTXS (SSD_RST) - Sleep(1) - _SB.PCI0.CTXS (SSD_EN) - } }
/* Method called from _WAK prior to wakeup */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 4b05ba8..41121d2 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -15,8 +15,6 @@
#define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -#define SSD_EN GPP_H13 -#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -37,13 +35,6 @@
/* Clear touch screen pd pin to avoid leakage */ _SB.PCI0.CTXS (TS_PD) - - /* Clear SSD EN adn RST pin to avoid leakage */ - If (Arg0 == 5) { - _SB.PCI0.CTXS (SSD_RST) - Sleep(1) - _SB.PCI0.CTXS (SSD_EN) - } }
/* Method called from _WAK prior to wakeup */
Bora Guvendik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33410 )
Change subject: mb/google/{sarien,arcada} Fix SSD's power off sequence before going to S5 ......................................................................
Abandoned
Not needed anymore
-
Bora Guvendik (Code Review)