[S] Change in coreboot[master]: sociintel/(adl, cmn, mtl): Refactor cse_fw_sync() function

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74582 )

Change subject: sociintel/(adl, cmn, mtl): Refactor cse_fw_sync() function
......................................................................

sociintel/(adl, cmn, mtl): Refactor cse_fw_sync() function

This patch refactors cse_fw_sync() function to include timestamp
associated with the CSE sync operation.This effort will ensure the
SoC code just makes a call into the cse_fw_sync() without bothering
about adding timestamp entries.

TEST=Able to build and boot google/marasov.

Signed-off-by: Subrata Banik 
Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/meteorlake/romstage/romstage.c
3 files changed, 28 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74582/1

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index a3273e6..740a4a2 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -180,11 +180,8 @@
    if (!CONFIG(INTEL_TXT))
    	disable_intel_txt();

-	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
-		timestamp_add_now(TS_CSE_FW_SYNC_START);
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake)
    	cse_fw_sync();
-		timestamp_add_now(TS_CSE_FW_SYNC_END);
-	}

/* Program to Disable UFS Controllers */
    if (!is_devfn_enabled(PCH_DEVFN_UFS) &&
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 1e2a052..14a7381 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1077,7 +1077,7 @@
    return handle_cse_sub_part_fw_update_rv(rv);
 }

-void cse_fw_sync(void)
+static void do_cse_fw_sync(void)
 {
    static struct get_bp_info_rsp cse_bp_info;

@@ -1152,6 +1152,13 @@
    }
 }

+void cse_fw_sync(void)
+{
+	timestamp_add_now(TS_CSE_FW_SYNC_START);
+	do_cse_fw_sync();
+	timestamp_add_now(TS_CSE_FW_SYNC_END);
+}
+
 static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id,
    struct fw_version_resp *resp)
 {
@@ -1214,11 +1221,8 @@
    if (acpi_get_sleep_type() == ACPI_S3)
    	return;

-	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) {
-		timestamp_add_now(TS_CSE_FW_SYNC_START);
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE))
    	cse_fw_sync();
-		timestamp_add_now(TS_CSE_FW_SYNC_END);
-	}
 }

BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_fw_sync, NULL);
diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index ebb440c..b5351de 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -128,11 +128,8 @@
    /* Initialize HECI interface */
    cse_init(HECI1_BASE_ADDRESS);

-	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
-		timestamp_add_now(TS_CSE_FW_SYNC_START);
+	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU))
    	cse_fw_sync();
-		timestamp_add_now(TS_CSE_FW_SYNC_END);
-	}

/* Update coreboot timestamp table with CSE timestamps */
    if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))