Change in coreboot[master]: mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblock

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel.
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Paul Menzel, Fred Reitberger,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/61903

to look at the new patch set (#3).

Change subject: mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblock
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mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblock

The SPI ROM REQ/GNT pins are used in systems where the EC and the APU
share one flash chip to make sure that not both devices will try to
access the flash at the same time. The firmware running before the x86
cores are released from reset has likely already done this, but do it
again in bootblock just to be sure. The KBRST_L pin can be used to reset
the APU from the EC.

Signed-off-by: Felix Held 
Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f
---
M src/mainboard/amd/chausie/early_gpio.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/61903/3