HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44850 )
Change subject: SMBIOS: Update smbios.h ......................................................................
SMBIOS: Update smbios.h
Type 9: add PCI Express Gen 5. add OCP NIC. add Slot Type extensions for PCIe Gen6. add support for CXL 2.0. add EDSFF slot types
Type 17: add new memory device types DDR5 and LPDDR5
Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/include/smbios.h 1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44850/1
diff --git a/src/include/smbios.h b/src/include/smbios.h index 521339e..a91f6a6 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -174,6 +174,8 @@ MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, MEMORY_TYPE_HBM = 0x20, MEMORY_TYPE_HBM2 = 0x21, + MEMORY_TYPE_DDR5 = 0x22, + MEMORY_TYPE_LPDDR5 = 0x23, } smbios_memory_type;
typedef enum { @@ -664,6 +666,11 @@ SlotTypePciExpressMini52pinWithBSKO = 0x21, SlotTypePciExpressMini52pinWithoutBSKO = 0x22, SlotTypePciExpressMini76pin = 0x23, + SlotTypePciExpressGen4SFF8639 = 0x24, + SlotTypePciExpressGen5SFF8639 = 0x25, + SlotTypeOcpNic3SFF = 0x26, + SlotTypeOcpNic3LFF = 0x27, + SlotTypeOcpNicPriorTo3 = 0x28, SlotTypePC98C20 = 0xA0, SlotTypePC98C24 = 0xA1, SlotTypePC98E = 0xA2, @@ -692,7 +699,16 @@ SlotTypePciExpressGen4x2 = 0xBA, SlotTypePciExpressGen4x4 = 0xBB, SlotTypePciExpressGen4x8 = 0xBC, - SlotTypePciExpressGen4x16 = 0xBD + SlotTypePciExpressGen4x16 = 0xBD, + SlotTypePciExpressGen5 = 0xBE, + SlotTypePciExpressGen5x1 = 0xBF, + SlotTypePciExpressGen5x2 = 0xC0, + SlotTypePciExpressGen5x4 = 0xC1, + SlotTypePciExpressGen5x8 = 0xC2, + SlotTypePciExpressGen5x16 = 0xC3, + SlotTypePciExpressGen6 = 0xC4, + SlotTypeEDSFFE1 = 0xC5, + SlotTypeEDSFFE3 0xC6 };
/* System Slots - Slot Data Bus Width. */ @@ -744,6 +760,9 @@ #define SMBIOS_SLOT_HOTPLUG (1 << 1) #define SMBIOS_SLOT_SMBUS (1 << 2) #define SMBIOS_SLOT_BIFURCATION (1 << 3) +#define SMBIOS_SLOT_ASYNC (1 << 4) +#define SMBIOS_SLOT_CXL_1 (1 << 5) +#define SMBIOS_SLOT_CXL_2 (1 << 6)
struct slot_peer_groups { u16 peer_seg_num;
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44850
to look at the new patch set (#2).
Change subject: SMBIOS: Update smbios.h ......................................................................
SMBIOS: Update smbios.h
Type 9: add PCI Express Gen 5. add OCP NIC. add Slot Type extensions for PCIe Gen6. add support for CXL 2.0. add EDSFF slot types
Type 17: add new memory device types DDR5 and LPDDR5
Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/include/smbios.h 1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44850/2
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44850
to look at the new patch set (#3).
Change subject: SMBIOS: Update smbios.h ......................................................................
SMBIOS: Update smbios.h
Type 9: add PCI Express Gen 5. add OCP NIC. add Slot Type extensions for PCIe Gen6. add CXL 2.0. add EDSFF slot types
Type 17: add new memory device types DDR5 and LPDDR5
Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/include/smbios.h 1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44850/3
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44850
to look at the new patch set (#4).
Change subject: SMBIOS: Update smbios.h ......................................................................
SMBIOS: Update smbios.h
Update according to SMBIOS specification version 3.4.0 Date: 2020-07-17
Type 9: add PCI Express Gen 5. add OCP NIC. add Slot Type extensions for PCIe Gen6. add CXL 2.0. add EDSFF slot types
Type 17: add new memory device types DDR5 and LPDDR5
Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/include/smbios.h 1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44850/4
Attention is currently required from: HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44850 )
Change subject: SMBIOS: Update smbios.h ......................................................................
Patch Set 5: Code-Review+1
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44850 )
Change subject: SMBIOS: Update smbios.h ......................................................................
Abandoned
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)