Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35767 )
Change subject: mediatek/mt8183: Improve DRAM calibration logs ......................................................................
mediatek/mt8183: Improve DRAM calibration logs
Several info logs are changed to debug logs (which are disabled by default). A few info messages are also improved for readability.
Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 27 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35767/1
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index a194d7a..7a7cf94 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -73,7 +73,7 @@ clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); udelay(1);
- dramc_show("K DRVP\n"); + dramc_dbg("K DRVP\n"); setbits_le32(&ch[0].ao.impcal, 0x1 << 23); setbits_le32(&ch[0].ao.impcal, 0x1 << 22); clrbits_le32(&ch[0].ao.impcal, 0x1 << 21); @@ -88,18 +88,18 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("1. OCD DRVP=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n", + impx_drv, imp_cal_result);
if (imp_cal_result == 1 && DRVP_result == 0xff) { DRVP_result = impx_drv; - dramc_show("1. OCD DRVP calibration OK! DRVP=%d\n", - DRVP_result); + dramc_dbg("1. OCD DRVP calibration OK! DRVP=%d\n", + DRVP_result); break; } }
- dramc_show("K ODTN\n"); + dramc_dbg("K ODTN\n"); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN); clrbits_le32(&ch[0].ao.impcal, 0x1 << 22); if (term == ODT_ON) @@ -116,21 +116,21 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("3. OCD ODTN=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n", + impx_drv, imp_cal_result);
if (imp_cal_result == 0 && ODTN_result == 0xff) { ODTN_result = impx_drv; - dramc_show("3. OCD ODTN calibration OK! ODTN=%d\n", - ODTN_result); + dramc_dbg("3. OCD ODTN calibration OK! ODTN=%d\n", + ODTN_result); break; } }
write32(&ch[0].ao.impcal, impcal_bak);
- dramc_show("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n", - term, DRVP_result, DRVN_result, ODTN_result); + dramc_dbg("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n", + term, DRVP_result, DRVN_result, ODTN_result); if (term == ODT_OFF) { impedance[term][0] = DRVP_result; impedance[term][1] = ODTN_result; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index fcc3b14..527d394 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1024,14 +1024,14 @@ }
for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], - best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], + best_coarse_tune0p5t[dqs], best_fine_tune[dqs]);
for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], - best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d P1 dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], + best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]);
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); @@ -1181,7 +1181,7 @@ mask, tmp); break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1294,7 +1294,7 @@ *end = *begin + 64; break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1421,7 +1421,7 @@ break;
default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; }
@@ -2003,7 +2003,7 @@ u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { - dramc_show("Start K ch:%d, rank:%d\n", chn, rk); + dramc_dbg("Start K: ch=%d, rank=%d\n", chn, rk); dramc_auto_refresh_switch(chn, false); dramc_cmd_bus_training(chn, rk, freq_group, pams); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 8bd8a39..08710ce 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -343,10 +343,12 @@
static void do_calib(const struct sdram_params *params, u8 freq_group) { - dramc_show("Start K freq group:%d\n", frequency_table[freq_group]); + dramc_show("Starting calibration (freq=%d)\n", + frequency_table[freq_group]); dramc_calibrate_all_channels(params, freq_group); dramc_ac_timing_optimize(freq_group); - dramc_show("%s K freq group:%d finish!\n", __func__, frequency_table[freq_group]); + dramc_show("Calibration finished (freq=%d)\n", + frequency_table[freq_group]); }
static void after_calib(void) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 1ce5f67..f10d8fa 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -20,6 +20,7 @@ #include <soc/emi.h> #include <console/console.h>
+#define dramc_err(_x_...) printk(BIOS_ERR, _x_) #define dramc_show(_x_...) printk(BIOS_INFO, _x_) #if CONFIG(DEBUG_DRAM) #define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_)
Hello Julius Werner, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35767
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8183: Improve DRAM calibration logs ......................................................................
soc/mediatek/mt8183: Improve DRAM calibration logs
Several info logs are changed to debug logs. A few info messages are also improved for readability.
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot
Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 23 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35767/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35767 )
Change subject: soc/mediatek/mt8183: Improve DRAM calibration logs ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35767/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/35767/2/src/soc/mediatek/mt8183/dra... PS2, Line 96: DRVP_result); Format changes should be done in separate commits.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35767 )
Change subject: soc/mediatek/mt8183: Improve DRAM calibration logs ......................................................................
Patch Set 2:
agree, we should put format/indent-only changes into a separate commit, since there are real function changes in this commit.
Hello Julius Werner, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35767
to look at the new patch set (#3).
Change subject: soc/mediatek/mt8183: Improve DRAM calibration logs ......................................................................
soc/mediatek/mt8183: Improve DRAM calibration logs
- Add macro dramc_err. - Some log levels are changed. - Some messages are improved for readability.
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot
Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 19 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35767/3
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35767 )
Change subject: soc/mediatek/mt8183: Improve DRAM calibration logs ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35767/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/35767/2/src/soc/mediatek/mt8183/dra... PS2, Line 96: DRVP_result);
Format changes should be done in separate commits.
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35767 )
Change subject: soc/mediatek/mt8183: Improve DRAM calibration logs ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35767 )
Change subject: soc/mediatek/mt8183: Improve DRAM calibration logs ......................................................................
soc/mediatek/mt8183: Improve DRAM calibration logs
- Add macro dramc_err. - Some log levels are changed. - Some messages are improved for readability.
BRANCH=kukui BUG=none TEST=emerge-kukui coreboot
Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu yupingso@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35767 Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 19 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index d4a1d59..eb30381 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -128,8 +128,8 @@
write32(&ch[0].ao.impcal, impcal_bak);
- dramc_show("impedance: term=%d, DRVP=%d, DRVN=%d, ODTN=%d\n", - term, DRVP_result, DRVN_result, ODTN_result); + dramc_dbg("impedance: term=%d, DRVP=%d, DRVN=%d, ODTN=%d\n", + term, DRVP_result, DRVN_result, ODTN_result); u32 *imp = impedance->data[term]; if (term == ODT_OFF) { imp[0] = DRVP_result; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 0c45ea0..ab92a7c 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1036,14 +1036,14 @@ }
for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], - best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], + best_coarse_tune0p5t[dqs], best_fine_tune[dqs]);
for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], - best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d P1 dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], + best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]);
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); @@ -1189,7 +1189,7 @@ SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, val); break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1302,7 +1302,7 @@ *end = *begin + 64; break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1429,7 +1429,7 @@ break;
default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; }
@@ -1997,7 +1997,7 @@
*test_passed = (sum != 0); if (!*test_passed) { - dramc_show("DRAM memory test failed\n"); + dramc_err("DRAM memory test failed\n"); return 0; }
@@ -2118,8 +2118,8 @@ u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { - dramc_show("Start K: freq=%d, ch=%d, rank=%d\n", - freq_group, chn, rk); + dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", + freq_group, chn, rk); dramc_cmd_bus_training(chn, rk, freq_group, pams, fast_calib); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 653253f..0e068cd 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -434,7 +434,7 @@ if (src_shuffle == dst_shuffle) return;
- dramc_show("Save shuffle %u to shuffle %u\n", src_shuffle, dst_shuffle); + dramc_dbg("Save shuffle %u to shuffle %u\n", src_shuffle, dst_shuffle);
for (chn = 0; chn < CHANNEL_MAX; chn++) { /* DRAMC */ @@ -449,7 +449,6 @@
} } - dramc_show("the dramc register of chn %d saved!\n", chn);
/* DRAMC-exception-1 */ src_addr = (u8 *)&ch[chn].ao.shuctrl2; @@ -461,8 +460,6 @@ else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) clrsetbits_le32(dst_addr, 0x7f << 0x16, value << 0x16);
- dramc_show("the dramc exception-1 register of chn %d saved!\n", chn); - /* DRAMC-exception-2 */ src_addr = (u8 *)&ch[chn].ao.dvfsdll; value = (read32(src_addr) >> 1) & 0x1; @@ -472,8 +469,6 @@ else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) clrsetbits_le32(src_addr, 0x1 << 3, value << 3);
- dramc_show("the dramc exception-2 register of chn %d saved!\n", chn); - /* PHY */ for (index = 0; index < ARRAY_SIZE(phy_regs); index++) { for (offset = phy_regs[index].start; @@ -486,7 +481,6 @@
} } - dramc_show("the phy register of chn %d saved!\n", chn); } }
@@ -507,7 +501,7 @@ set_vcore_voltage(freq_group);
dramc_show("Run calibration (freq: %u, first: %d)\n", - freq_group, *first_run); + frequency_table[freq_group], *first_run);
if (*first_run) init_dram(params, freq_group, impedance); @@ -515,11 +509,11 @@ dfs_init_for_calibration(params, freq_group, impedance); *first_run = false;
- dramc_show("Start K (current clock: %u\n", params->frequency); + dramc_dbg("Start K (current clock: %u\n", params->frequency); if (dramc_calibrate_all_channels(params, freq_group) != 0) return -1; dramc_ac_timing_optimize(freq_group); - dramc_show("K finished (current clock: %u\n", params->frequency); + dramc_dbg("K finished (current clock: %u\n", params->frequency);
dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); return 0; diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 65ec075..40a516d 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -20,6 +20,7 @@ #include <soc/emi.h> #include <console/console.h>
+#define dramc_err(_x_...) printk(BIOS_ERR, _x_) #define dramc_show(_x_...) printk(BIOS_INFO, _x_) #if CONFIG(DEBUG_DRAM) #define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_)
-
Hung-Te Lin (Code Review) -
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Yu-Ping Wu (Code Review)