[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support

[ChiaLing (Code Review)]

Attention is currently required from: ChiaLing, Ryan Lin, Zhuohao Lee.

Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/75678?usp=email

to look at the new patch set (#3).

Change subject: soc/intel/common: Add PsysPl1 support
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soc/intel/common: Add PsysPl1 support

Set PsysPL1 in set_power_limits in order to increase
system performance for no battery design.

BUG=b:281479111
TEST=emerge-dedede coreboot and check PsysPl1 value on DUT

Signed-off-by: Chia-Ling Hou 
Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320
---
M src/soc/intel/common/block/include/intelblocks/power_limit.h
M src/soc/intel/common/block/power_limit/power_limit.c
2 files changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75678/3