[M] Change in coreboot[master]: mb/intel/mtlrvp: Add fmd for debug FSP

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74193 )

Change subject: mb/intel/mtlrvp: Add fmd for debug FSP
......................................................................

mb/intel/mtlrvp: Add fmd for debug FSP

Debug FSP is ~920KiB larger than release FSP and we don't have
sufficient space for MTL-P RVP flash layout.

Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.

BUG=b:271407315
TEST=Build intel/mtlrvp with CONFIG_BUILDING_WITH_DEBUG_FSP.

Change-Id: Ief7dd39af018c4c1519ca80d1303085d8298cda6
Signed-off-by: Usha P 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74193
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
Reviewed-by: Kapil Porwal 
Reviewed-by: Krishna P Bhat D 
---
M src/mainboard/intel/mtlrvp/Kconfig
A src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd
2 files changed, 79 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Krishna P Bhat D: Looks good to me, approved
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved

diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 0af0529..8a66ea0 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -70,6 +70,7 @@
    default "mtlrvp"

config FMDFILE
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
    default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"

config MAINBOARD_FAMILY
diff --git a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd
new file mode 100644
index 0000000..579a7bd
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd
@@ -0,0 +1,54 @@
+FLASH 32M {
+	SI_ALL 9M {
+		SI_DESC 16K
+		SI_ME
+	}
+	SI_BIOS 23M {
+		RW_SECTION_A 7M {
+			VBLOCK_A 64K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+			ME_RW_A(CBFS) 3008K
+		}
+		RW_MISC 1M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			# The RW_SPD_CACHE region is only used for variants that use DDRx memory.
+			# It is placed in the common `chromeos.fmd` file because it is only 4K and there
+			# is free space in the RW_MISC region that cannot be easily reclaimed because
+			# the RW_SECTION_B must start on the 16M boundary.
+			RW_SPD_CACHE(PRESERVE) 4K
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+		# This section starts at the 16M boundary in SPI flash.
+		# MTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 7M {
+			VBLOCK_B 64K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+			ME_RW_B(CBFS) 3008K
+		}
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 8M {
+			RO_VPD(PRESERVE) 16K
+			RO_GSCVD 8K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}