Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/21459 )

Change subject: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/21459/1//COMMIT_MSG
Commit Message:

https://review.coreboot.org/#/c/21459/1//COMMIT_MSG@9
PS1, Line 9: If LPSS UART port had been set up to hidden mode, FSP will not force
           : 8 bit transition mode (AKA 16550 compatible UART mode).
FSP should not force UART in 8 bit mode unless its Legacy UART configuration.If you see that after you set UART as PCI and still FSP is doing legacy 8 bit mode program then please raise a FSP bug and give me. I don't see such case and in my FSP code, i could see PChSerialIoSkip option which allow FSP to skip UART programming.

The problem with this CL is that, your kernel will unable to bind serial driver hence serial log or login console will be at risk.

I don't understand the point of digressing so much from SKL/KBL coreboot implementation for CNL when its same IP and no change in serial debug from SOC or BIOS.