Change in coreboot[master]: soc/intel/apollolake: defines constant for C1E enable mask

[Cole Nelson (Code Review)]

Cole Nelson has uploaded this change for review. ( https://review.coreboot.org/27035

Change subject: soc/intel/apollolake: defines constant for C1E enable mask
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soc/intel/apollolake: defines constant for C1E enable mask

Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E
enable bit.  Define POWER_CTL_C1E_MASK to be used subsequently.

Change-Id: I7a5408f6678f56540929b7811764845b6dad1149
Signed-off-by: Cole Nelson 
---
M src/soc/intel/common/block/include/intelblocks/msr.h
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/27035/1

diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 22e8862..e1fc431 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -72,6 +72,7 @@
 #define  PRMRR_PHYS_MASK_LOCK		(1 << 10)
 #define  PRMRR_PHYS_MASK_VALID		(1 << 11)
 #define MSR_POWER_CTL			0x1fc
+#define  POWER_CTL_C1E_MASK		(1 << 1)
 #define MSR_EVICT_CTL			0x2e0
 #define MSR_SGX_OWNEREPOCH0		0x300
 #define MSR_SGX_OWNEREPOCH1		0x301