Attention is currently required from: Zheng Bao. Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/61836
to review the following change.
Change subject: amdfwtool: Add options to support mainboard specific SPL table ......................................................................
amdfwtool: Add options to support mainboard specific SPL table
BUG=b:216096562
Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/61836/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1d5db12..4dee16e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1086,6 +1086,7 @@ AMDFW_OPT_USE_PSPSECUREOS, AMDFW_OPT_LOAD_MP2FW, AMDFW_OPT_LOAD_S0I3, + AMDFW_OPT_SPL_TABLE, AMDFW_OPT_VERSTAGE, AMDFW_OPT_VERSTAGE_SIG,
@@ -1131,6 +1132,7 @@ {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, + {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE }, {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, /* BIOS Directory Table items */ @@ -1463,6 +1465,11 @@ case AMDFW_OPT_LOAD_S0I3: cb_config.s0i3 = true; break; + case AMDFW_OPT_SPL_TABLE: + register_fw_filename(AMD_FW_SPL, sub, optarg); + sub = instance = 0; + cb_config.have_mb_spl = true; + break; case AMDFW_OPT_WHITELIST: register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); sub = instance = 0; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index b14a437..79e52fc 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -251,6 +251,7 @@ bool load_mp2_fw; bool multi_level; bool s0i3; + bool have_mb_spl; } amd_cb_config;
void register_fw_fuse(char *str); diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 6814346..106ea65 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -283,8 +283,12 @@ fw_type = AMD_FW_KEYDB_TOS; subprog = 0; } else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) { - fw_type = AMD_FW_SPL; - subprog = 0; + if (cb_config->have_mb_spl) { + fw_type = AMD_FW_SPL; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) { fw_type = AMD_FW_DMCU_ERAM; subprog = 0;