[S] Change in coreboot[master]: soc/intel/alderlake: Add/Remove LTR disqualification - coreboot-gerrit

10 Oct 2022


      Attention is currently required from: Tim Wawrzynczak.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 )
Change subject: soc/intel/alderlake: Add/Remove LTR disqualification
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c
Gerrit-Change-Number: 68251
Gerrit-PatchSet: 1
Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com
Gerrit-Reviewer: Tim Wawrzynczak inforichland@gmail.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Tim Wawrzynczak inforichland@gmail.com
Gerrit-Comment-Date: Mon, 10 Oct 2022 07:04:24 +0000
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