[L] Change in coreboot[master]: commonlib/console/post_code.h: Change post code prefix to POSTCODE

[Yuchen He (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Arthur Heymans, Boris Mittelberg, Caveh Jalali, Christian Walter, Felix Held, Felix Singer, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Johnny Lin, Julius Werner, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Raul Rangel, Subrata Banik, Tarun Tuli, Tim Chu, Werner Zeh, Yu-Ping Wu.

Hello Andrey Petrov, Angel Pons, Arthur Heymans, Boris Mittelberg, Caveh Jalali, Christian Walter, Felix Held, Felix Singer, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Johnny Lin, Julius Werner, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Raul Rangel, Subrata Banik, Tarun Tuli, Tim Chu, Werner Zeh, Yu-Ping Wu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/76043?usp=email

to look at the new patch set (#4).

Change subject: commonlib/console/post_code.h: Change post code prefix to POSTCODE
......................................................................

commonlib/console/post_code.h: Change post code prefix to POSTCODE

The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.

The files was changed by running the following bash script from the
top level directory.

sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
  src/commonlib/include/commonlib/console/post_codes.h;
  myArray=`grep -e "^#define POSTCODE_" \
  src/commonlib/include/commonlib/console/post_codes.h | \
  grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;

for str in ${myArray[@]}; do
    splitstr=`echo $str | cut -d '_' -f2-`
    grep -r POST_$splitstr src | \
    cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
    grep -r "POST_$splitstr" util/cbfstool | \
    cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
  done

Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious 
---
M src/arch/x86/acpi_s3.c
M src/arch/x86/c_start.S
M src/arch/x86/postcar_loader.c
M src/arch/x86/tables.c
M src/commonlib/include/commonlib/console/post_codes.h
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p3/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/cpu/x86/entry16.S
M src/cpu/x86/entry32.S
M src/device/device.c
M src/device/pci_device.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/intel/fsp1_1/cache_as_ram.S
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/pc80/rtc/post.c
M src/ec/google/wilco/commands.c
M src/lib/hardwaremain.c
M src/lib/prog_loaders.c
M src/lib/ramtest.c
M src/northbridge/intel/haswell/broadwell_mrc/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/vboot_logic.c
M src/soc/amd/cezanne/cpu.c
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/amd/common/block/cpu/smm/finalize.c
M src/soc/amd/glinda/cpu.c
M src/soc/amd/mendocino/cpu.c
M src/soc/amd/phoenix/cpu.c
M src/soc/amd/picasso/cpu.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/meteorlake/finalize.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/tigerlake/finalize.c
M src/soc/intel/xeon_sp/finalize.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/i82801gx/lpc.c
M src/vendorcode/google/chromeos/cr50_enable_update.c
M util/cbfstool/eventlog.c
68 files changed, 234 insertions(+), 234 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/76043/4