Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42644 )
Change subject: sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT` ......................................................................
sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT`
Most other Intel southbridges call those `TPSV` and `TCRT` instead.
Change-Id: Id4c30cd53abc544b743eb80696bfafe45929208e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/nvs.h 2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42644/1
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 34c550c..3b6115f 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -36,11 +36,11 @@ /* Thermal policy */ Offset (0x14), ACTT, 8, // 0x14 - active trip point - PSVT, 8, // 0x15 - passive trip point + TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 TC2V, 8, // 0x17 - passive trip point TC2 TSPV, 8, // 0x18 - passive trip point TSP - CRTT, 8, // 0x19 - critical trip point + TCRT, 8, // 0x19 - critical trip point DTSE, 8, // 0x1a - Digital Thermal Sensor enable DTS1, 8, // 0x1b - DT sensor 1 FLVL, 8, // 0x1c - current fan level diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 8dd012f..6b697f2 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -22,11 +22,11 @@ u8 dckn; /* 0x13 - PCIe docking state */ /* Thermal policy */ u8 actt; /* 0x14 - active trip point */ - u8 psvt; /* 0x15 - passive trip point */ + u8 tpsv; /* 0x15 - passive trip point */ u8 tc1v; /* 0x16 - passive trip point TC1 */ u8 tc2v; /* 0x17 - passive trip point TC2 */ u8 tspv; /* 0x18 - passive trip point TSP */ - u8 crtt; /* 0x19 - critical trip point */ + u8 tcrt; /* 0x19 - critical trip point */ u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ u8 dts1; /* 0x1b - DT sensor 1 */ u8 flvl; /* 0x1c - current fan level */
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42644 )
Change subject: sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT` ......................................................................
Patch Set 2: Code-Review+2
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42644 )
Change subject: sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT` ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42644 )
Change subject: sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT` ......................................................................
sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT`
Most other Intel southbridges call those `TPSV` and `TCRT` instead.
Change-Id: Id4c30cd53abc544b743eb80696bfafe45929208e Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42644 Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Frans Hendriks fhendriks@eltan.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/nvs.h 2 files changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Frans Hendriks: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 34c550c..3b6115f 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -36,11 +36,11 @@ /* Thermal policy */ Offset (0x14), ACTT, 8, // 0x14 - active trip point - PSVT, 8, // 0x15 - passive trip point + TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 TC2V, 8, // 0x17 - passive trip point TC2 TSPV, 8, // 0x18 - passive trip point TSP - CRTT, 8, // 0x19 - critical trip point + TCRT, 8, // 0x19 - critical trip point DTSE, 8, // 0x1a - Digital Thermal Sensor enable DTS1, 8, // 0x1b - DT sensor 1 FLVL, 8, // 0x1c - current fan level diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 8dd012f..6b697f2 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -22,11 +22,11 @@ u8 dckn; /* 0x13 - PCIe docking state */ /* Thermal policy */ u8 actt; /* 0x14 - active trip point */ - u8 psvt; /* 0x15 - passive trip point */ + u8 tpsv; /* 0x15 - passive trip point */ u8 tc1v; /* 0x16 - passive trip point TC1 */ u8 tc2v; /* 0x17 - passive trip point TC2 */ u8 tspv; /* 0x18 - passive trip point TSP */ - u8 crtt; /* 0x19 - critical trip point */ + u8 tcrt; /* 0x19 - critical trip point */ u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ u8 dts1; /* 0x1b - DT sensor 1 */ u8 flvl; /* 0x1c - current fan level */
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Angel Pons (Code Review) -
Frans Hendriks (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)