Change in coreboot[master]: soc/intel/jasperlake: add pcie modphy settings

[Jamie Chen (Code Review)]

Attention is currently required from: Jamie Chen.
Hello Jamie Chen,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/56336

to review the following change.

Change subject: soc/intel/jasperlake: add pcie modphy settings
......................................................................

soc/intel/jasperlake: add pcie modphy settings

This patch expose some pcie modphy UPDs/configuration
to be filled from devicetree. It's for fine tune pcie
port signal quality.

BUG=b:192716633
BRANCH=NONE
TEST=build dedede variant coreboot with fw_debug enable and chekc if
these settings have been changed successfully on fsp debug log.

Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831
Signed-off-by: Jamie Chen 
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/romstage/fsp_params.c
2 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/56336/1

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 36e9a13..1e6a300 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -101,6 +101,22 @@
    uint8_t PchHdaIDispLinkFrequency;
    uint8_t PchHdaIDispCodecDisconnect;

+	/* PCIe ModPHY related */
+	uint8_t PchPcieHsioRxSetCtleEnable[24];
+	uint8_t PchPcieHsioRxSetCtle[24];
+	uint8_t PchPcieHsioTxGen1DownscaleAmpEnable[24];
+	uint8_t PchPcieHsioTxGen1DownscaleAmp[24];
+	uint8_t PchPcieHsioTxGen2DownscaleAmpEnable[24];
+	uint8_t PchPcieHsioTxGen2DownscaleAmp[24];
+	uint8_t PchPcieHsioTxGen3DownscaleAmpEnable[24];
+	uint8_t PchPcieHsioTxGen3DownscaleAmp[24];
+	uint8_t PchPcieHsioTxGen1DeEmphEnable[24];
+	uint8_t PchPcieHsioTxGen1DeEmph[24];
+	uint8_t PchPcieHsioTxGen2DeEmph3p5Enable[24];
+	uint8_t PchPcieHsioTxGen2DeEmph3p5[24];
+	uint8_t PchPcieHsioTxGen2DeEmph6p0Enable[24];
+	uint8_t PchPcieHsioTxGen2DeEmph6p0[24];
+
    /* PCIe Root Ports */
    uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
    /* PCIe output clocks type to PCIe devices.
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index c1208e3..4c2c925 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -27,6 +27,30 @@
    m_cfg->SaGv = config->SaGv;
    m_cfg->RMT = config->RMT;

+	/* PCIe ModPhy configuration */
+	for (i = 0; i < ARRAY_SIZE(config->PchPcieHsioRxSetCtleEnable); i++) {
+		if (config->PchPcieHsioRxSetCtleEnable[i])
+			m_cfg->PchPcieHsioRxSetCtle[i] = config->PchPcieHsioRxSetCtle[i];
+		if (config->PchPcieHsioTxGen1DownscaleAmpEnable[i])
+			m_cfg->PchPcieHsioTxGen1DownscaleAmp[i] =
+				config->PchPcieHsioTxGen1DownscaleAmp[i];
+		if (config->PchPcieHsioTxGen2DownscaleAmpEnable[i])
+			m_cfg->PchPcieHsioTxGen2DownscaleAmp[i] =
+				config->PchPcieHsioTxGen2DownscaleAmp[i];
+		if (config->PchPcieHsioTxGen3DownscaleAmp[i])
+			m_cfg->PchPcieHsioTxGen3DownscaleAmp[i] =
+				config->PchPcieHsioTxGen3DownscaleAmp[i];
+		if (config->PchPcieHsioTxGen1DeEmphEnable[i])
+			m_cfg->PchPcieHsioTxGen1DeEmph[i] =
+				config->PchPcieHsioTxGen1DeEmph[i];
+		if (config->PchPcieHsioTxGen2DeEmph3p5Enable[i])
+			m_cfg->PchPcieHsioTxGen2DeEmph3p5[i] =
+				config->PchPcieHsioTxGen2DeEmph3p5[i];
+		if (config->PchPcieHsioTxGen2DeEmph6p0Enable[i])
+			m_cfg->PchPcieHsioTxGen2DeEmph6p0[i] =
+				config->PchPcieHsioTxGen2DeEmph6p0[i];
+	}
+
    /* PCIe root port configuration */
    for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
    	if (config->PcieRpEnable[i])