Hello Seunghwan Kim,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34397
to review the following change.
Change subject: mb/google/kohaku: Update DPTF parameters ......................................................................
mb/google/kohaku: Update DPTF parameters
Apply initial DPTF parameters for kohaku. The main perpose of this change is adjusting PL1, and we need further fine tuning later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl 1 file changed, 54 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34397/1
diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl index f1f0943..0db8bea 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -13,4 +13,57 @@ * GNU General Public License for more details. */
-#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 5000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +})
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: The main perpose of this change is adjusting PL1, and we need further fine tuning later. Please wrap the line.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: perpose purpose
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 64: 51000 Shouldn't this match tdp_pl2_override? That seems to be set to 52W and not 51W here: https://review.coreboot.org/c/coreboot/+/34398/1/src/mainboard/google/hatch/...
Also, can you please squash the two changes into one CL? They should be really going in together.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 63: 51000 Any reason for keeping PowerLimit Minimum and Maximum (below) to same value 51W ?
SH Kim has uploaded a new patch set (#2) to the change originally created by shkim. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters ......................................................................
mb/google/kohaku: Update DPTF parameters
Apply initial DPTF parameters for kohaku.
The main purpose of this change is adjusting PL1, and we need further fine tuning later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl 1 file changed, 54 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34397/2
Hello Seunghwan Kim, Sumeet R Pawnikar, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34397
to look at the new patch set (#3).
Change subject: mb/google/kohaku: Update DPTF parameters ......................................................................
mb/google/kohaku: Update DPTF parameters
Apply initial DPTF parameters for kohaku.
The main purpose of this change is adjusting PL1, and we need further fine tuning later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34397/3
Hello Seunghwan Kim, Sumeet R Pawnikar, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34397
to look at the new patch set (#4).
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2
Update DPTF parameters and TDP PL1/PL2 values for kohaku.
The main purpose of this change is adjusting PL1 and PL2, and we need further fine tuning later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34397/4
shkim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: The main perpose of this change is adjusting PL1, and we need further fine tuning later.
Please wrap the line.
Done
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: perpose
purpose
Done
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 63: 51000
Any reason for keeping PowerLimit Minimum and Maximum (below) to same value 51W ?
As I know PL2 setting in DPTF table doesn't work. DUT just sets PL2 with "tdp_pl2_override" value and chrome DPTF does not change PL2 value in runtime. I changed this to just indicate current setting. Please let me know if I have misunderstanding.
PL2 51W is recommended value for CML-U system with 8W TDP design. I got this value from a document from Intel (I don't remember what it was exactly, but we used this value in TPnP camp; b:136138567).
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 64: 51000
Shouldn't this match tdp_pl2_override? That seems to be set to 52W and not 51W here: https://review. […]
Done
shkim has removed Seunghwan Kim from this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Removed reviewer Seunghwan Kim.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4:
Sumeet, do you have any concerns here?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4: Code-Review+1
Waiting for input from Sumeet to +2 this.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 63: 51000
As I know PL2 setting in DPTF table doesn't work. […]
Please, add me in this b:136138567, would like to check the document and review this. Thanks.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 63: 51000
Please, add me in this b:136138567, would like to check the document and review this. Thanks.
Done.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4: Code-Review+2
I have checked the bug and this CL looks good.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 4:
(2 comments)
It’s quite hard to review this change. The commit message should be more elaborate.
https://review.coreboot.org/c/coreboot/+/34397/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34397/4//COMMIT_MSG@11 PS4, Line 11: The main purpose of this change is adjusting PL1 and PL2, : and we need further fine tuning later. Please use the full textwidth.
https://review.coreboot.org/c/coreboot/+/34397/4//COMMIT_MSG@9 PS4, Line 9: Update DPTF parameters and TDP PL1/PL2 values for kohaku. : : The main purpose of this change is adjusting PL1 and PL2, : and we need further fine tuning later. What are you achieving with the update?
Adjust PL1 and PL2 to …. More fine-tuning will happen later.
SH Kim has uploaded a new patch set (#5) to the change originally created by shkim. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2
Update DPTF parameters and TDP PL1/PL2 values for kohaku.
Since kohaku has been designed as TDP 8W, we need to limit PL1 setting to 8W. And 51W is the recommended PL2 value for CML-U TDP 8W design, we would take it.
More fine-tuning will happen later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34397/5
SH Kim has uploaded a new patch set (#6) to the change originally created by shkim. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2
Update DPTF parameters and TDP PL1/PL2 values for kohaku.
Since kohaku has been designed as TDP 8W, we need to limit PL1 setting to 8W. And 51W is the recommended PL2 value for CML-U TDP 8W design, we would take it.
More fine-tuning will happen later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34397/6
SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 6:
+ Grace, Ben @ Intel Just got first DPTF tuning result from Intel TW team, I would apply it as initial parameters. https://partnerissuetracker.corp.google.com/issues/136138567
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 6: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34397/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/34397/6/src/mainboard/google/hatch/... PS6, Line 2: 8 does this need to be updated to 15 now?
SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34397/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/34397/6/src/mainboard/google/hatch/... PS6, Line 2: 8
does this need to be updated to 15 now?
I don't think so. We might use 8W PL1 in case of DPTF not working.
SH Kim has uploaded a new patch set (#7) to the change originally created by shkim. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34397/7
SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 7:
And I'd like to remove any model specific information (e.g. TDP design) on public commit message. Is it okay?
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 7:
Patch Set 7:
And I'd like to remove any model specific information (e.g. TDP design) on public commit message. Is it okay?
I feel that okay.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 7: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 7: Code-Review+2
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 7:
(5 comments)
Resolving all comments for submission.
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: The main perpose of this change is adjusting PL1, and we need further fine tuning later.
Done
Done
https://review.coreboot.org/c/coreboot/+/34397/1//COMMIT_MSG@10 PS1, Line 10: perpose
Done
Done
https://review.coreboot.org/c/coreboot/+/34397/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34397/4//COMMIT_MSG@9 PS4, Line 9: Update DPTF parameters and TDP PL1/PL2 values for kohaku. : : The main purpose of this change is adjusting PL1 and PL2, : and we need further fine tuning later.
What are you achieving with the update? […]
Done
https://review.coreboot.org/c/coreboot/+/34397/4//COMMIT_MSG@11 PS4, Line 11: The main purpose of this change is adjusting PL1 and PL2, : and we need further fine tuning later.
Please use the full textwidth.
Done
https://review.coreboot.org/c/coreboot/+/34397/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/34397/6/src/mainboard/google/hatch/... PS6, Line 2: 8
I don't think so. We might use 8W PL1 in case of DPTF not working.
Done
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
Patch Set 7:
(1 comment)
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34397/1/src/mainboard/google/hatch/... PS1, Line 63: 51000
Done.
Done
Shelley Chen has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34397 )
Change subject: mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2 ......................................................................
mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later.
BUG=b:1704071 BRANCH=none TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim sh_.kim@samsung.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397 Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 57 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl index f1f0943..06df7b1 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -13,4 +13,57 @@ * GNU General Public License for more details. */
-#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 8000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 250 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index e463b8b..fa64d60 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "8" + register "tdp_pl2_override" = "51" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,
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Furquan Shaikh (Code Review) -
Paul Menzel (Code Review)
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SH Kim (Code Review)
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Shelley Chen (Code Review)
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shkim (Code Review)
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Sumeet R Pawnikar (Code Review)