Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14902
-gerrit
commit 5617465f7ea356560501fb7bcead28fa0631eee7 Author: Akshay Saraswat akshay.s@samsung.com Date: Thu Aug 7 14:07:12 2014 +0530
Add support for Exynos7 SoC
Adding new directory and corresponding files in soc/samsung for new SoC version Exynos7 to provide basic boot support.
BUG=None BRANCH=None TEST=Compiled and booted coreboot over Jazz with this series
Change-Id: I21fc956e88d754311c74eec0313ca833f9e33b14 Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- src/soc/samsung/exynos7/Kconfig | 136 +++++++++++++++++++ src/soc/samsung/exynos7/Makefile.inc | 36 +++++ src/soc/samsung/exynos7/bootblock.c | 33 +++++ src/soc/samsung/exynos7/cpu.c | 43 ++++++ .../samsung/exynos7/include/soc/bootblock_exynos.h | 21 +++ src/soc/samsung/exynos7/include/soc/cpu.h | 151 +++++++++++++++++++++ src/soc/samsung/exynos7/include/soc/periph.h | 67 +++++++++ src/soc/samsung/exynos7/memlayout.ld | 37 +++++ 8 files changed, 524 insertions(+)
diff --git a/src/soc/samsung/exynos7/Kconfig b/src/soc/samsung/exynos7/Kconfig new file mode 100644 index 0000000..db2b063 --- /dev/null +++ b/src/soc/samsung/exynos7/Kconfig @@ -0,0 +1,136 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Samsung Electronics +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_SAMSUNG_EXYNOS7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select RELOCATABLE_MODULES + select BOOTBLOCK_CONSOLE + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + bool + default n + +if SOC_SAMSUNG_EXYNOS7 + +config BOOTBLOCK_CPU_INIT + default "soc/samsung/exynos7/include/soc/bootblock_exynos.h" + +# ROM image layout. +# +# 0x0000: vendor-provided BL1 (8k). +# 0x2000: variable length bootblock checksum header +# 0x2010: bootblock +# 0x9F80-0xA000: reserved for CBFS master header. +# 0xA000: Free for CBFS data. + +config BOOTBLOCK_ROM_OFFSET + hex + default 0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0xBF80 + +config CBFS_ROM_OFFSET + # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size. + hex "offset of CBFS data in ROM" + default 0x0C000 + +config SYS_SDRAM_BASE + hex + default 0x40000000 + +# Example SRAM/iRAM map for Exynos7 platform: +# +# 0x0210_0000: Reserved for device specific information. +# 0x0210_1800: Samsung trusted BL1. +# 0x0210_3800: Reserved for secure contents. +# 0x0210_4000: Variable length bootblock checksum header. +# 0x0210_4010: Bootblock, assume up to 64KB in size +# 0x0211_4000: Romstage, assume up to 176KB in size. +# 0x0214_0000: TTB buffer, 64KB in size. +# 0x0214_8000: Romstage Stack Bottom. +# 0x0214_C000: Romstage Stack Top. +# 0x0215_0000: Generic Stack Top. +# 0xF000_0000: Cache for CBFS data, 1M in size. + +config BOOTBLOCK_BASE + hex + default 0x02104010 + +config ROMSTAGE_BASE + hex + default 0x02114000 + +config RAMSTAGE_BASE + hex + default SYS_SDRAM_BASE + +config CBFS_CACHE_ADDRESS + hex "memory address to put CBFS cache data" + default 0xF0000000 + +config CBFS_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00100000 + +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0x02140000 + +config TTB_SIZE + hex "size of the TTB buffer" + default 0x10000 + +choice CONSOLE_SERIAL_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_UART2 + depends on DRIVERS_UART + +config CONSOLE_SERIAL_UART0 + bool "UART0" + help + Serial console on UART0 + +config CONSOLE_SERIAL_UART1 + bool "UART1" + help + Serial console on UART1 + +config CONSOLE_SERIAL_UART2 + bool "UART2" + help + Serial console on UART2 + +config CONSOLE_SERIAL_UART3 + bool "UART3" + help + Serial console on UART3 + +endchoice + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0x13630000 if CONSOLE_SERIAL_UART0 + default 0x14c20000 if CONSOLE_SERIAL_UART1 + default 0x14c30000 if CONSOLE_SERIAL_UART2 + default 0x14c40000 if CONSOLE_SERIAL_UART3 + help + Map the UART names to the respective MMIO address. + +endif diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc new file mode 100644 index 0000000..11d0fd3 --- /dev/null +++ b/src/soc/samsung/exynos7/Makefile.inc @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Samsung Electronics +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_SAMSUNG_EXYNOS7),y) + +CPPFLAGS_common += -Isrc/soc/samsung/exynos7/include/ + +# BOOTBLOCK : UART related and minimum required hardware init +bootblock-y += bootblock.c + +# ROMSTAGE : Run primitive tests and remaining basic stuff + +# RAMSTAGE : Prepare and load payload +ramstage-y += cpu.c + +$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf + cp $< $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" + util/exynos/variable_cksum.py $< $<.cksum size_in_blocks sha256 + cat 3rdparty/cpu/samsung/exynos7/bl1.bin $<.cksum > $@ + +endif diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c new file mode 100644 index 0000000..7336392 --- /dev/null +++ b/src/soc/samsung/exynos7/bootblock.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <arch/clock.h> +#include <bootblock_common.h> +#include <stdlib.h> + +#include <soc/cpu.h> + +void bootblock_cpu_init(void) +{ + /* SCR_EL3.NS|IRQ|FIQ|EA */ + raw_write_scr_el3(raw_read_scr_el3() | 0xf); + + /* Enable FP/SIMD */ + raw_write_cptr_el3(0); + + /* Set Counter Frequency */ + set_cntfrq(EXYNOS7_COUNTER_FREQ); +} diff --git a/src/soc/samsung/exynos7/cpu.c b/src/soc/samsung/exynos7/cpu.c new file mode 100644 index 0000000..476e973 --- /dev/null +++ b/src/soc/samsung/exynos7/cpu.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> +#include <console/console.h> +#include <device/device.h> +#include <cbmem.h> +#include <arch/cache.h> +#include <soc/cpu.h> + +static struct device_operations cpu_ops = { + .read_resources = NULL, + .set_resources = NULL, + .enable_resources = NULL, + .init = NULL, + .scan_bus = NULL, +}; + +static void enable_exynos7_dev(device_t dev) +{ + /* DUMMY: Add stuff when required */ + dev->ops = &cpu_ops; +} + +struct chip_operations soc_samsung_exynos7_ops = { + CHIP_NAME("Samsung Exynos") + .enable_dev = enable_exynos7_dev, +}; diff --git a/src/soc/samsung/exynos7/include/soc/bootblock_exynos.h b/src/soc/samsung/exynos7/include/soc/bootblock_exynos.h new file mode 100644 index 0000000..f881d03 --- /dev/null +++ b/src/soc/samsung/exynos7/include/soc/bootblock_exynos.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPU_SAMSUNG_BOOTBLOCK_EXYNOS_H_ +#define _CPU_SAMSUNG_BOOTBLOCK_EXYNOS_H_ + +void bootblock_cpu_init(void); + +#endif /* _CPU_SAMSUNG_BOOTBLOCK_EXYNOS7_H_ */ diff --git a/src/soc/samsung/exynos7/include/soc/cpu.h b/src/soc/samsung/exynos7/include/soc/cpu.h new file mode 100644 index 0000000..513938f --- /dev/null +++ b/src/soc/samsung/exynos7/include/soc/cpu.h @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPU_SAMSUNG_EXYNOS7_CPU_H_ +#define _CPU_SAMSUNG_EXYNOS7_CPU_H_ + +#include <arch/io.h> + +#define AP_PPN 0xD07 +#define EXYNOS7_SRAM_BASE 0x02100000 +#define EXYNOS7_COUNTER_FREQ 0x1800000 +#define EXYNOS7_CHECK_SLEEP 0x00000BAD +#define PHY_IRAM_BASE 0x02100000 +#define COREBOOT_RESERVED 0x50000 +#define PHY_IRAM_NS_BASE (PHY_IRAM_BASE \ + + COREBOOT_RESERVED \ + + 0xb000) + +/* Base address registers */ +#define EXYNOS7_PRO_ID 0x10000000 +#define EXYNOS7_PMU_PERIS_BASE 0x10010000 +#define EXYNOS7_CMU_PERIS_BASE 0x10040000 +#define EXYNOS7_SYSREG_BASE 0x10050000 +#define EXYNOS7_TMU_BASE 0x10060000 +#define EXYNOS7_TZPC_BASE 0x10100000 +#define EXYNOS7_MCT_BASE 0x101C0000 +#define EXYNOS7_WATCHDOG_AP_BASE 0x101D0000 +#define EXYNOS7_CMU_TOPC_BASE 0x10570000 +#define EXYNOS7_GPIO_ALIVE_BASE 0x10580000 +#define EXYNOS7_CMU_CCORE_BASE 0x105B0000 +#define EXYNOS7_PMU_ALIVE_BASE 0x105C0000 +#define EXYNOS7_SWRESET 0x105C0400 +#define EXYNOS7_CMU_TOP0_BASE 0x105D0000 +#define EXYNOS7_CMU_TOP1_BASE 0x105E0000 +#define EXYNOS7_PMU_CCORE_BASE 0x105F0000 +#define EXYNOS7_DMC_DREX0_BASE 0x10800000 +#define EXYNOS7_DMC_ASP0_BASE 0x10810000 +#define EXYNOS7_DMC_PHY0_BASE 0x10820000 +#define EXYNOS7_PMU_MIF0_BASE 0x10840000 +#define EXYNOS7_CMU_MIF0_BASE 0x10850000 +#define EXYNOS7_DMC_VTMON0_BASE 0x10890000 +#define EXYNOS7_DMC_DREX1_BASE 0x10900000 +#define EXYNOS7_DMC_ASP1_BASE 0x10910000 +#define EXYNOS7_DMC_PHY1_BASE 0x10920000 +#define EXYNOS7_PMU_MIF1_BASE 0x10940000 +#define EXYNOS7_CMU_MIF1_BASE 0x10950000 +#define EXYNOS7_DMC_VTMON1_BASE 0x10990000 +#define EXYNOS7_DMC_DREX2_BASE 0x10A00000 +#define EXYNOS7_DMC_ASP2_BASE 0x10A10000 +#define EXYNOS7_DMC_PHY2_BASE 0x10A20000 +#define EXYNOS7_PMU_MIF2_BASE 0x10A40000 +#define EXYNOS7_CMU_MIF2_BASE 0x10A50000 +#define EXYNOS7_DMC_VTMON2_BASE 0x10A90000 +#define EXYNOS7_DMC_DREX3_BASE 0x10B00000 +#define EXYNOS7_DMC_ASP3_BASE 0x10B10000 +#define EXYNOS7_DMC_PHY3_BASE 0x10B20000 +#define EXYNOS7_PMU_MIF3_BASE 0x10B40000 +#define EXYNOS7_CMU_MIF3_BASE 0x10B50000 +#define EXYNOS7_DMC_VTMON3_BASE 0x10B90000 +#define EXYNOS7_GPIO_FSYS0_BASE 0x10E60000 +#define EXYNOS7_PMU_FSYS0_BASE 0x10E70000 +#define EXYNOS7_CMU_FSYS0_BASE 0x10E90000 +#define EXYNOS7_GIC_BASE 0x11000000 +#define EXYNOS7_CMU_IMEM_BASE 0x11060000 +#define EXYNOS7_PMU_IMEM_BASE 0x11070000 +#define EXYNOS7_MI2S_BASE 0x11440000 +#define EXYNOS7_GPIO_AUD_BASE 0x114B0000 +#define EXYNOS7_CMU_AUD_BASE 0x114C0000 +#define EXYNOS7_PMU_AUD_BASE 0x114D0000 +#define EXYNOS7_CMU_AP_BASE 0x11800000 +#define EXYNOS7_PMU_AP_BASE 0x11820000 +#define EXYNOS7_MMC_BASE 0x12200000 +#define EXYNOS7_CMU_G2D_BASE 0x12460000 +#define EXYNOS7_PMU_G2D_BASE 0x12470000 +#define EXYNOS7_CMU_BUS0_BASE 0x13400000 +#define EXYNOS7_PMU_BUS0_BASE 0x13420000 +#define EXYNOS7_GPIO_BUS0_BASE 0x13470000 +#define EXYNOS7_PMU_PERIC0_BASE 0x13600000 +#define EXYNOS7_CMU_PERIC0_BASE 0x13610000 +#define EXYNOS7_UART00_BASE 0x13630000 +#define EXYNOS7_HSI2C0_BASE 0x13640000 +#define EXYNOS7_HSI2C1_BASE 0x13650000 +#define EXYNOS7_HSI2C4_BASE 0x13660000 +#define EXYNOS7_HSI2C5_BASE 0x13670000 +#define EXYNOS7_HSI2C9_BASE 0x13680000 +#define EXYNOS7_HSI2C10_BASE 0x13690000 +#define EXYNOS7_HSI2C11_BASE 0x136A0000 +#define EXYNOS7_PWMTIMER_BASE 0x136C0000 +#define EXYNOS7_CMU_DISP_BASE 0x13AD0000 +#define EXYNOS7_CMU_VPP_BASE 0x13ED0000 +#define EXYNOS7_PMU_VPP_BASE 0x13EE0000 +#define EXYNOS7_CMU_ISP0_LOCAL_BASE 0x14290000 +#define EXYNOS7_CMU_ISP1_LOCAL_BASE 0x142F0000 +#define EXYNOS7_PMU_DISP_BASE 0x145E0000 +#define EXYNOS7_CMU_ISP0_BASE 0x146D0000 +#define EXYNOS7_PMU_ISP0_BASE 0x146E0000 +#define EXYNOS7_CMU_ISP1_BASE 0x147D0000 +#define EXYNOS7_PMU_ISP1_BASE 0x147E0000 +#define EXYNOS7_CMU_BUS1_BASE 0x14800000 +#define EXYNOS7_PMU_BUS1_BASE 0x14820000 +#define EXYNOS7_GPIO_BUS1_BASE 0x14870000 +#define EXYNOS7_PMU_G3D_BASE 0x14A40000 +#define EXYNOS7_CMU_G3D_BASE 0x14AA0000 +#define EXYNOS7_UART10_BASE 0x14C20000 +#define EXYNOS7_UART11_BASE 0x14C30000 +#define EXYNOS7_UART12_BASE 0x14C40000 +#define EXYNOS7_PMU_PERIC1_BASE 0x14C70000 +#define EXYNOS7_CMU_PERIC1_BASE 0x14C80000 +#define EXYNOS7_GPIO_FF_BASE 0x14C90000 +#define EXYNOS7_GPIO_ESE_BASE 0x14CA0000 +#define EXYNOS7_GPIO_PERIC_BASE 0x14CC0000 +#define EXYNOS7_GPIO_NFC_BASE 0x14CD0000 +#define EXYNOS7_GPIO_TOUCH_BASE 0x14CE0000 +#define EXYNOS7_SPI0_BASE 0x14D20000 +#define EXYNOS7_SPI1_BASE 0x14D30000 +#define EXYNOS7_SPI2_BASE 0x14D40000 +#define EXYNOS7_SPI3_BASE 0x14D50000 +#define EXYNOS7_MI2S_V51_BASE 0x14D60000 +#define EXYNOS7_SPI4_BASE 0x14D70000 +#define EXYNOS7_HSI2C6_BASE 0x14E00000 +#define EXYNOS7_HSI2C7_BASE 0x14E10000 +#define EXYNOS7_HSI2C8_BASE 0x14E20000 +#define EXYNOS7_HSI2C2_BASE 0x14E60000 +#define EXYNOS7_HSI2C3_BASE 0x14E70000 +#define EXYNOS7_CMU_HEVC_BASE 0x14F80000 +#define EXYNOS7_PMU_HEVC_BASE 0x14F90000 +#define EXYNOS7_CMU_MSCL_BASE 0x150D0000 +#define EXYNOS7_PMU_MSCL_BASE 0x150F0000 +#define EXYNOS7_CMU_MFC_BASE 0x15280000 +#define EXYNOS7_PMU_MFC_BASE 0x15290000 +#define EXYNOS7_USB_DRD0_DWC3_BASE 0x15400000 +#define EXYNOS7_USB_DRD1_DWC3_BASE 0x15500000 +#define EXYNOS7_USB_DRD0_PHY_BASE 0x15510000 +#define EXYNOS7_USB_HOST_PHY_BASE 0x15530000 +#define EXYNOS7_GPIO_FSYS1_BASE 0x15690000 +#define EXYNOS7_PMU_FSYS1_BASE 0x156C0000 +#define EXYNOS7_CMU_FSYS1_BASE 0x156E0000 + +#endif /* _CPU_SAMSUNG_EXYNOS7_CPU_H_ */ diff --git a/src/soc/samsung/exynos7/include/soc/periph.h b/src/soc/samsung/exynos7/include/soc/periph.h new file mode 100644 index 0000000..1492ee2 --- /dev/null +++ b/src/soc/samsung/exynos7/include/soc/periph.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CPU_SAMSUNG_EXYNOS7_PERIPH_H +#define CPU_SAMSUNG_EXYNOS7_PERIPH_H + +/* + * Peripherals requiring clock/pinmux configuration. List will + * grow with support for more devices getting added. + * + * At present the order is arbitrary - we may be able to take advantage + * of some orthogonality later. + */ +enum periph_id { + PERIPH_ID_UART0, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_LCD, + PERIPH_ID_BACKLIGHT, + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_I2C8, + PERIPH_ID_I2C9, + PERIPH_ID_I2C10, + PERIPH_ID_I2C11, + PERIPH_ID_DPHPD, /* eDP hot plug detect */ + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2S1, + PERIPH_ID_SATA, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +#endif diff --git a/src/soc/samsung/exynos7/memlayout.ld b/src/soc/samsung/exynos7/memlayout.ld new file mode 100644 index 0000000..ef6e3ec --- /dev/null +++ b/src/soc/samsung/exynos7/memlayout.ld @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Note: The BootROM loads the 8K BL1 at [0x2101800:0x2103800), so the bootblock + * must be placed after that. After the handoff, the space can be reclaimed. + */ + +SECTIONS +{ + SRAM_START(0x2100000) + /* 16K hole, includes BL1 */ + /* Bootblock is preceeded by 16 byte variable length BL2 checksum. */ + BOOTBLOCK(0x2104010, 64K - 16) + ROMSTAGE(0x2114000, 176K) + STACK(0x2150000, 32K) + SRAM_END(0x2160000) + DRAM_START(0x40000000) + RAMSTAGE(0x40000000, 256K) + CBFS_CACHE(0xf0000000, 1M) +}
-
Stefan Reinauer