Change in coreboot[master]: soc/intel/alderlake: Hook up common code for thermal configuration
Attention is currently required from: Felix Singer, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59271 )
Change subject: soc/intel/alderlake: Hook up common code for thermal configuration ......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59271/comment/9395e5de_9549cb23 PS3, Line 7: Allow thermal configuration
How about this: […]
Ack
https://review.coreboot.org/c/coreboot/+/59271/comment/6e544da0_7faa0cab PS3, Line 7: for ADL
Not needed. Already mentioned in the first part.
Ack
Patchset:
PS3:
Do we need this as early as possible? Like rom-stage before MRC training to prevent some HW issue?
We might need do this prior to FSP-S otherwise FSP-S will perform those thermal register lockdown and it would result RO while coreeboot attempts to perform thermal configuration. Hence, coreboot decides to perform thermal configuration prior FSP-S starts its execution and disallow FSP to override those settings.
You can find some details in commit msg as well
Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform.
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Subrata Banik (Code Review)