Patch set updated for coreboot: 8664f83 exynos5420: ddr3: Cleanup init to use constants for directcmd

[Isaac Christensen]

Isaac Christensen ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6605

-gerrit

commit 8664f833619d439b91aceccace281f7ec2f02860
Author: David Hendricks 
Date:   Thu Aug 22 18:45:10 2013 -0700

exynos5420: ddr3: Cleanup init to use constants for directcmd

The old ddr3_mem_ctrl_init() for exynos5420 had hardcoded constants
    for accessing directcmd registers.  Modify to use #defines where
    possible.

This is ported from: https://gerrit.chromium.org/gerrit/#/c/65616
    Signed-off-by: David Hendricks

Change-Id: I01567fc6941608a570832de97259c55e84942d01
    Reviewed-on: https://gerrit.chromium.org/gerrit/66789
    Commit-Queue: David Hendricks 
    Tested-by: David Hendricks 
    Reviewed-by: Ronald G. Minnich 
    (cherry picked from commit d751e019f450172f060ce255ae53e972bc4a19ea)
    Signed-off-by: Isaac Christensen 
---
 src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 37 +++++++++++++++++-------------
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 0a4edc8..6c774a0 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -264,10 +264,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
    	nLockR |= nLockW_phy1;
    	writel(nLockR, &phy1_ctrl->phy_con12);

-		writel(0x00030004, &drex0->directcmd);
-		writel(0x00130004, &drex0->directcmd);
-		writel(0x00030004, &drex1->directcmd);
-		writel(0x00130004, &drex1->directcmd);
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+		writel(val, &drex0->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
+		writel(val, &drex1->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);

setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
    	setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
@@ -316,16 +317,19 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
    	writel(0, &phy0_ctrl->phy_con14);
    	writel(0, &phy1_ctrl->phy_con14);

-		writel(0x00030000, &drex0->directcmd);
-		writel(0x00130000, &drex0->directcmd);
-		writel(0x00030000, &drex1->directcmd);
-		writel(0x00130000, &drex1->directcmd);
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+		writel(val, &drex0->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
+		writel(val, &drex1->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);

/* Set Read DQ Calibration */
-		writel(0x00030004, &drex0->directcmd);
-		writel(0x00130004, &drex0->directcmd);
-		writel(0x00030004, &drex1->directcmd);
-		writel(0x00130004, &drex1->directcmd);
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+		writel(val, &drex0->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
+		writel(val, &drex1->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
+

val = readl(&phy0_ctrl->phy_con1);
    	val |= READ_LEVELLING_DDR3;
@@ -371,10 +375,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
    		return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
    	clrbits_le32(&drex1->rdlvl_config, CTRL_RDLVL_DATA_ENABLE);

-		writel(0x00030000, &drex0->directcmd);
-		writel(0x00130000, &drex0->directcmd);
-		writel(0x00030000, &drex1->directcmd);
-		writel(0x00130000, &drex1->directcmd);
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+		writel(val, &drex0->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
+		writel(val, &drex1->directcmd);
+		writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);

update_reset_dll(drex0, DDR_MODE_DDR3);
    	update_reset_dll(drex1, DDR_MODE_DDR3);