Change in coreboot[master]: cpu/x86/smm: Promote smm_memory_map()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34792 )

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki 
---
M configs/config.intel_galileo_gen2.debug
M src/cpu/intel/car/romstage.c
M src/cpu/x86/smm/tseg_region.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/mainboard/intel/galileo/Kconfig
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/common/Kconfig
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
11 files changed, 41 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34792/1

diff --git a/configs/config.intel_galileo_gen2.debug b/configs/config.intel_galileo_gen2.debug
index ceea7d0..f4fdb2d 100644
--- a/configs/config.intel_galileo_gen2.debug
+++ b/configs/config.intel_galileo_gen2.debug
@@ -3,7 +3,6 @@
 CONFIG_BOARD_INTEL_GALILEO=y
 # CONFIG_FSP_DEBUG_ALL is not set
 CONFIG_DISPLAY_MTRRS=y
-CONFIG_DISPLAY_SMM_MEMORY_MAP=y
 CONFIG_DISPLAY_ESRAM_LAYOUT=y
 CONFIG_BOOTBLOCK_NORMAL=y
 CONFIG_ON_DEVICE_ROM_LOAD=y
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 89052d6..59ee720 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -15,6 +15,7 @@
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <arch/symbols.h>
 #include <commonlib/helpers.h>
 #include <program_loading.h>
@@ -52,6 +53,9 @@
    	printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
    }

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    platform_enter_postcar();
 }

diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c
index e225fa5..49864cd 100644
--- a/src/cpu/x86/smm/tseg_region.c
+++ b/src/cpu/x86/smm/tseg_region.c
@@ -70,6 +70,24 @@
    return 0;
 }

+void smm_list_regions(void)
+{
+	uintptr_t base;
+	size_t size;
+	int i;
+
+	printk(BIOS_DEBUG, "SMM Memory Map\n");
+
+	smm_region(&base, &size);
+	printk(BIOS_DEBUG, "SMRAM       : 0x%zx 0x%zx\n", base, size);
+
+	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
+		if (smm_subregion(i, &base, &size))
+			continue;
+		printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
+	}
+}
+
 void stage_cache_external_region(void **base, size_t *size)
 {
    if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 4b567da..57068cf 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -30,25 +30,6 @@
 {
 }

-/* Display SMM memory map */
-static void smm_memory_map(void)
-{
-	uintptr_t base;
-	size_t size;
-	int i;
-
-	printk(BIOS_SPEW, "SMM Memory Map\n");
-
-	smm_region(&base, &size);
-	printk(BIOS_SPEW, "SMRAM       : 0x%zx 0x%zx\n", base, size);
-
-	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
-		if (smm_subregion(i, &base, &size))
-			continue;
-		printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
-	}
-}
-
 static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
 {
    const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
@@ -147,9 +128,6 @@

static void fsp_cache_save(struct prog *fsp)
 {
-	if (CONFIG(DISPLAY_SMM_MEMORY_MAP))
-		smm_memory_map();
-
    if (CONFIG(NO_STAGE_CACHE))
    	return;

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 79a6ff5..2c41c12 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -604,4 +604,7 @@
  * 0 on success, < 0 on failure. */
 int smm_subregion(int sub, uintptr_t *start, size_t *size);

+/* Print the SMM memory layout on console. */
+void smm_list_regions(void);
+
 #endif /* CPU_X86_SMM_H */
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index 0f49c7f..e7e95e7 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -95,7 +95,6 @@
 # Enable display and verification for coreboot build tests
    select DISPLAY_HOBS
    select DISPLAY_MTRRS
-	select DISPLAY_SMM_MEMORY_MAP
    select DISPLAY_UPD_DATA
    select DISPLAY_ESRAM_LAYOUT
    select DISPLAY_FSP_CALLS_AND_STATUS
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 7e2bb64..b1d5fb3 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
@@ -129,6 +130,9 @@
    /* Call into mainboard. */
    mainboard_romstage_entry(&rp);

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    platform_enter_postcar();

/* We don't return here */
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 523d1f5..44c2392 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -15,10 +15,6 @@
 comment "Intel SoC Common coreboot stages"
 source "src/soc/intel/common/basecode/Kconfig"

-config DISPLAY_SMM_MEMORY_MAP
-	bool "SMM: Display the SMM memory map"
-	default n
-
 config SOC_INTEL_COMMON_RESET
    bool
    default n
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 52f4dc9..35b531a 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -24,6 +24,7 @@
 #include <console/usb.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
@@ -255,9 +256,11 @@

romstage_handoff_init(prev_sleep_state == ACPI_S3);

-	post_code(0x4f);
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();

/* Load the ramstage. */
+	post_code(0x4f);
    run_ramstage();
    while (1);
 }
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 38cd947..638f1ed 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <console/usb.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <timestamp.h>
 #include <version.h>
@@ -120,6 +121,9 @@
    	die("Could not allocate cbmem for HOB pointer");
    *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr;

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    /* Load the ramstage. */
    post_code(0x4e);
    run_ramstage();
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 2c2427e..f52a752 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -31,6 +31,7 @@
 #include "southbridge/intel/fsp_rangeley/gpio.h"
 #include "southbridge/intel/fsp_rangeley/romstage.h"
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include "gpio.h"

void main(FSP_INFO_HEADER *fsp_info_header)
@@ -121,9 +122,11 @@
    *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
    post_code(0x4e);

-	post_code(0x4f);
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();

/* Load the ramstage. */
+	post_code(0x4f);
    run_ramstage();
    while (1);
 }

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34792

to look at the new patch set (#5).

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki 
---
M configs/config.intel_galileo_gen2.debug
M src/cpu/intel/car/romstage.c
M src/cpu/x86/smm/tseg_region.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/mainboard/intel/galileo/Kconfig
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/common/Kconfig
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
11 files changed, 42 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34792/5

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Huang Jin, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34792

to look at the new patch set (#6).

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki 
---
M configs/config.intel_galileo_gen2.debug
M src/cpu/intel/car/romstage.c
M src/cpu/x86/smm/tseg_region.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/mainboard/intel/galileo/Kconfig
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/common/Kconfig
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
11 files changed, 41 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34792/6

[Kyösti Mälkki (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34792

to look at the new patch set (#7).

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki 
---
M configs/config.intel_galileo_gen2.debug
M src/cpu/intel/car/romstage.c
M src/cpu/x86/smm/tseg_region.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/mainboard/intel/galileo/Kconfig
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/common/Kconfig
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
11 files changed, 43 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34792/7

[Kyösti Mälkki (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34792

to look at the new patch set (#8).

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki 
---
M configs/config.intel_galileo_gen2.debug
M src/cpu/intel/car/romstage.c
M src/cpu/x86/smm/tseg_region.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/mainboard/intel/galileo/Kconfig
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/common/Kconfig
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
13 files changed, 49 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34792/8

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34792 )

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

Patch Set 8: Code-Review+2

[Kyösti Mälkki (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Huang Jin, Arthur Heymans, Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34792

to look at the new patch set (#9).

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki 
---
M configs/config.intel_galileo_gen2.debug
M src/cpu/intel/car/romstage.c
M src/cpu/x86/smm/tseg_region.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/mainboard/intel/galileo/Kconfig
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/common/Kconfig
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
13 files changed, 49 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34792/9

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34792 )

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

Patch Set 10: Code-Review+2

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34792 )

Change subject: cpu/x86/smm: Promote smm_memory_map()
......................................................................

cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792
Reviewed-by: Aaron Durbin 
Tested-by: build bot (Jenkins) 
---
M configs/config.intel_galileo_gen2.debug
M src/cpu/intel/car/romstage.c
M src/cpu/x86/smm/tseg_region.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/mainboard/intel/galileo/Kconfig
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/common/Kconfig
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/intel/fsp_rangeley/romstage.c
13 files changed, 49 insertions(+), 30 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/configs/config.intel_galileo_gen2.debug b/configs/config.intel_galileo_gen2.debug
index ceea7d0..f4fdb2d 100644
--- a/configs/config.intel_galileo_gen2.debug
+++ b/configs/config.intel_galileo_gen2.debug
@@ -3,7 +3,6 @@
 CONFIG_BOARD_INTEL_GALILEO=y
 # CONFIG_FSP_DEBUG_ALL is not set
 CONFIG_DISPLAY_MTRRS=y
-CONFIG_DISPLAY_SMM_MEMORY_MAP=y
 CONFIG_DISPLAY_ESRAM_LAYOUT=y
 CONFIG_BOOTBLOCK_NORMAL=y
 CONFIG_ON_DEVICE_ROM_LOAD=y
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 624f3ff..43fbe8a 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -15,6 +15,7 @@
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <arch/symbols.h>
 #include <commonlib/helpers.h>
 #include <program_loading.h>
@@ -69,6 +70,9 @@
    	printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
    }

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    prepare_and_run_postcar(&early_mtrrs);
    /* We do not return here. */
 }
diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c
index df9dea5..07789f4 100644
--- a/src/cpu/x86/smm/tseg_region.c
+++ b/src/cpu/x86/smm/tseg_region.c
@@ -84,3 +84,23 @@
    	*size = 0;
    }
 }
+
+void smm_list_regions(void)
+{
+	uintptr_t base;
+	size_t size;
+	int i;
+
+	smm_region(&base, &size);
+	if (!size)
+		return;
+
+	printk(BIOS_DEBUG, "SMM Memory Map\n");
+	printk(BIOS_DEBUG, "SMRAM       : 0x%zx 0x%zx\n", base, size);
+
+	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
+		if (smm_subregion(i, &base, &size))
+			continue;
+		printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
+	}
+}
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 4b567da..57068cf 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -30,25 +30,6 @@
 {
 }

-/* Display SMM memory map */
-static void smm_memory_map(void)
-{
-	uintptr_t base;
-	size_t size;
-	int i;
-
-	printk(BIOS_SPEW, "SMM Memory Map\n");
-
-	smm_region(&base, &size);
-	printk(BIOS_SPEW, "SMRAM       : 0x%zx 0x%zx\n", base, size);
-
-	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
-		if (smm_subregion(i, &base, &size))
-			continue;
-		printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
-	}
-}
-
 static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
 {
    const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
@@ -147,9 +128,6 @@

static void fsp_cache_save(struct prog *fsp)
 {
-	if (CONFIG(DISPLAY_SMM_MEMORY_MAP))
-		smm_memory_map();
-
    if (CONFIG(NO_STAGE_CACHE))
    	return;

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index c338744..d8b9efe 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -160,4 +160,7 @@
  * 0 on success, < 0 on failure. */
 int smm_subregion(int sub, uintptr_t *start, size_t *size);

+/* Print the SMM memory layout on console. */
+void smm_list_regions(void);
+
 #endif /* CPU_X86_SMM_H */
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index c3d846c..7e1742d 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -94,7 +94,6 @@
 # Enable display and verification for coreboot build tests
    select DISPLAY_HOBS
    select DISPLAY_MTRRS
-	select DISPLAY_SMM_MEMORY_MAP
    select DISPLAY_UPD_DATA
    select DISPLAY_ESRAM_LAYOUT
    select DISPLAY_FSP_CALLS_AND_STATUS
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index dae64cc..22b5ce4 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -67,6 +67,9 @@
    if (romstage_handoff_init(s3_resume))
    	printk(BIOS_ERR, "Failed to set romstage handoff data\n");

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    post_code(0x44);
    if (postcar_frame_init(&pcf, 1 * KiB))
    	die("Unable to initialize postcar frame.\n");
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 42b0833..4cadc68 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -152,6 +152,9 @@
    if (romstage_handoff_init(s3_resume))
    	printk(BIOS_ERR, "Failed to set romstage handoff data\n");

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    post_code(0x44);
    if (postcar_frame_init(&pcf, 0))
    	die("Unable to initialize postcar frame.\n");
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 8361bb1..6bf8aac 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
@@ -146,6 +147,9 @@
    /* Call into mainboard. */
    mainboard_romstage_entry(&rp);

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    prepare_and_run_postcar(&early_mtrrs);
    /* We do not return here. */
 }
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 523d1f5..44c2392 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -15,10 +15,6 @@
 comment "Intel SoC Common coreboot stages"
 source "src/soc/intel/common/basecode/Kconfig"

-config DISPLAY_SMM_MEMORY_MAP
-	bool "SMM: Display the SMM memory map"
-	default n
-
 config SOC_INTEL_COMMON_RESET
    bool
    default n
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 52f4dc9..35b531a 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -24,6 +24,7 @@
 #include <console/usb.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
@@ -255,9 +256,11 @@

romstage_handoff_init(prev_sleep_state == ACPI_S3);

-	post_code(0x4f);
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();

/* Load the ramstage. */
+	post_code(0x4f);
    run_ramstage();
    while (1);
 }
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 3b74a1c..1f71c98 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <console/usb.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <timestamp.h>
 #include <version.h>
@@ -169,6 +170,9 @@
    if (!CONFIG(FSP_MEMORY_DOWN))
    	save_dimm_info();

+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
    /* Load the ramstage. */
    post_code(0x4e);
    run_ramstage();
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 2c2427e..f52a752 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -31,6 +31,7 @@
 #include "southbridge/intel/fsp_rangeley/gpio.h"
 #include "southbridge/intel/fsp_rangeley/romstage.h"
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include "gpio.h"

void main(FSP_INFO_HEADER *fsp_info_header)
@@ -121,9 +122,11 @@
    *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
    post_code(0x4e);

-	post_code(0x4f);
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();

/* Load the ramstage. */
+	post_code(0x4f);
    run_ramstage();
    while (1);
 }