New patch to review for coreboot: 0dda769 ipq806x: Change all SoC headers to <soc/headername.h> system
Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9368
-gerrit
commit 0dda769dacab60ef538459cbabb828d5cb42c871 Author: Julius Werner jwerner@chromium.org Date: Mon Oct 20 13:20:49 2014 -0700
ipq806x: Change all SoC headers to <soc/headername.h> system
This patch aligns ipq806x to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway.
BUG=None TEST=Tested with whole series. Compiled Storm.
Change-Id: Icb81a77e6f458625f5379a980e8760388dd3a1f9 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 1bf23774c9ffa5d08c211f3658d39adcfa47b339 Original-Change-Id: I283cc7e6094be977d67ed4146f376cebcea6774a Original-Signed-off-by: Julius Werner jwerner@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/224502 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/storm/boardid.c | 2 +- src/mainboard/google/storm/cdp.c | 4 +- src/mainboard/google/storm/mainboard.c | 7 +- src/mainboard/google/storm/memlayout.ld | 2 +- src/soc/qualcomm/ipq806x/Makefile.inc | 2 + src/soc/qualcomm/ipq806x/clock.c | 2 +- src/soc/qualcomm/ipq806x/gpio.c | 4 +- src/soc/qualcomm/ipq806x/include/cdp.h | 137 ----------- src/soc/qualcomm/ipq806x/include/clock.h | 196 --------------- src/soc/qualcomm/ipq806x/include/gpio.h | 110 --------- src/soc/qualcomm/ipq806x/include/gsbi.h | 35 --- src/soc/qualcomm/ipq806x/include/iomap.h | 110 --------- src/soc/qualcomm/ipq806x/include/ipq_timer.h | 40 --- src/soc/qualcomm/ipq806x/include/ipq_uart.h | 271 --------------------- src/soc/qualcomm/ipq806x/include/soc/cdp.h | 139 +++++++++++ src/soc/qualcomm/ipq806x/include/soc/clock.h | 196 +++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/gpio.h | 110 +++++++++ src/soc/qualcomm/ipq806x/include/soc/gsbi.h | 35 +++ src/soc/qualcomm/ipq806x/include/soc/iomap.h | 110 +++++++++ src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h | 40 +++ src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h | 271 +++++++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 40 +++ src/soc/qualcomm/ipq806x/include/soc/spi.h | 282 ++++++++++++++++++++++ src/soc/qualcomm/ipq806x/include/soc/usb.h | 26 ++ src/soc/qualcomm/ipq806x/include/spi.h | 282 ---------------------- src/soc/qualcomm/ipq806x/include/usb.h | 26 -- src/soc/qualcomm/ipq806x/memlayout.ld | 40 --- src/soc/qualcomm/ipq806x/spi.c | 6 +- src/soc/qualcomm/ipq806x/timer.c | 4 +- src/soc/qualcomm/ipq806x/uart.c | 10 +- src/soc/qualcomm/ipq806x/usb.c | 9 +- 31 files changed, 1275 insertions(+), 1273 deletions(-)
diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 683b5f4..a8dd844 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <stdlib.h> #include <boardid.h> #include <gpiolib.h> #include <console/console.h> +#include <stdlib.h>
/* * Storm boards dedicate to the board ID three GPIOs in tertiary mode: 29, 30 diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 94845c7..7e1aeb6 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -1,9 +1,9 @@
/* * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.* */
+#include <soc/gpio.h> +#include <soc/cdp.h> #include <types.h> -#include <cdp.h> -#include <gpio.h>
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) { diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 478e2a8..acadce5 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -24,13 +24,12 @@ #include <delay.h> #include <device/device.h> #include <gpiolib.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/usb.h> #include <string.h> #include <symbols.h>
-#include <soc/qualcomm/ipq806x/include/clock.h> -#include <soc/qualcomm/ipq806x/include/gpio.h> -#include <soc/qualcomm/ipq806x/include/usb.h> - /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram / MiB) #define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) diff --git a/src/mainboard/google/storm/memlayout.ld b/src/mainboard/google/storm/memlayout.ld index 1735835..ead7f47 100644 --- a/src/mainboard/google/storm/memlayout.ld +++ b/src/mainboard/google/storm/memlayout.ld @@ -1 +1 @@ -#include <soc/qualcomm/ipq806x/memlayout.ld> +#include <soc/memlayout.ld> diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 5dfca4d..6ee925c 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -40,6 +40,8 @@ ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += usb.c
+INCLUDES += -Isrc/soc/qualcomm/ipq806x/include/ + ifeq ($(CONFIG_USE_BLOBS),y)
# Generate the actual coreboot bootblock code diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index ee2ed64..fe7cfb8 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -3,8 +3,8 @@ */
#include <delay.h> +#include <soc/clock.h> #include <types.h> -#include <clock.h>
/** * uart_pll_vote_clk_enable - enables PLL8 diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 8cce3ba..46dca4e 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -28,9 +28,9 @@ * SUCH DAMAGE. */
-#include <iomap.h> -#include <gpio.h> #include <arch/io.h> +#include <soc/gpio.h> +#include <soc/iomap.h>
/******************************************************* Function description: check for invalid GPIO # diff --git a/src/soc/qualcomm/ipq806x/include/cdp.h b/src/soc/qualcomm/ipq806x/include/cdp.h deleted file mode 100644 index 15f91cb..0000000 --- a/src/soc/qualcomm/ipq806x/include/cdp.h +++ /dev/null @@ -1,137 +0,0 @@ -/* * Copyright (c) 2012 The Linux Foundation. All rights reserved.* */ - - -#ifndef _IPQ806X_CDP_H_ -#define _IPQ806X_CDP_H_ - -unsigned smem_get_board_machtype(void); - -typedef enum { - PHY_INTERFACE_MODE_MII, - PHY_INTERFACE_MODE_GMII, - PHY_INTERFACE_MODE_SGMII, - PHY_INTERFACE_MODE_QSGMII, - PHY_INTERFACE_MODE_TBI, - PHY_INTERFACE_MODE_RMII, - PHY_INTERFACE_MODE_RGMII, - PHY_INTERFACE_MODE_RGMII_ID, - PHY_INTERFACE_MODE_RGMII_RXID, - PHY_INTERFACE_MODE_RGMII_TXID, - PHY_INTERFACE_MODE_RTBI, - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_NONE /* Must be last */ -} phy_interface_t; - -typedef struct { - unsigned int gpio; - unsigned int func; - unsigned int dir; - unsigned int pull; - unsigned int drvstr; - unsigned int enable; -} gpio_func_data_t; - -typedef struct { - unsigned int m_value; - unsigned int n_value; - unsigned int d_value; -} uart_clk_mnd_t; - -/* SPI Mode */ - -typedef enum { - NOR_SPI_MODE_0, - NOR_SPI_MODE_1, - NOR_SPI_MODE_2, - NOR_SPI_MODE_3, -} spi_mode; - -/* SPI GSBI Bus number */ - -typedef enum { - GSBI_BUS_5 = 0, - GSBI_BUS_6, - GSBI_BUS_7, -} spi_gsbi_bus_num; - -/* SPI Chip selects */ - -typedef enum { - SPI_CS_0 , - SPI_CS_1, - SPI_CS_2, - SPI_CS_3, -} spi_cs; - -/* Flash Types */ - -typedef enum { - ONLY_NAND, - ONLY_NOR, - NAND_NOR, - NOR_MMC, -} flash_desc; - -#define NO_OF_DBG_UART_GPIOS 2 - -#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 -#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 - -/* SPI parameters */ - -typedef struct { - spi_mode mode; - spi_gsbi_bus_num bus_number; - spi_cs chip_select; - int vendor; -} spinorflash_params_t; - -typedef struct { - unsigned count; - uint8_t addr[7]; -} ipq_gmac_phy_addr_t; - -typedef struct { - unsigned base; - int unit; - unsigned is_macsec; - unsigned mac_pwr0; - unsigned mac_pwr1; - unsigned mac_conn_to_phy; - phy_interface_t phy; - ipq_gmac_phy_addr_t phy_addr; -} ipq_gmac_board_cfg_t; - -#define IPQ_GMAC_NMACS 4 - -/* Board specific parameters */ -typedef struct { -#if 0 - unsigned int gmac_gpio_count; - gpio_func_data_t *gmac_gpio; - ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; - flash_desc flashdesc; - spinorflash_params_t flash_param; -#endif -} __attribute__ ((__packed__)) board_ipq806x_params_t; - -extern board_ipq806x_params_t *gboard_param; - -#if 0 -static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) -{ - /* - * 'cfg' is valid if and only if - * unit number is non-negative and less than IPQ_GMAC_NMACS. - * 'cfg' pointer lies within the array range of - * board_ipq806x_params_t->gmac_cfg[] - */ - return ((cfg >= &gboard_param->gmac_cfg[0]) && - (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && - (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); -} -#endif - -unsigned int get_board_index(unsigned machid); -void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); -#endif diff --git a/src/soc/qualcomm/ipq806x/include/clock.h b/src/soc/qualcomm/ipq806x/include/clock.h deleted file mode 100644 index d9e7834..0000000 --- a/src/soc/qualcomm/ipq806x/include/clock.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. - * Source : APQ8064 LK Boot - * - * Copyright (c) 2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IPQ860X_CLOCK_H_ -#define __IPQ860X_CLOCK_H_ - -#include <iomap.h> - -/* UART clock @ 7.3728 MHz */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC - -/* UART specific definitions */ - -#define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) -#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) -#define Uart_mnd_en_mask BIT(8) * !!(625) -#define Uart_en_mask BIT(11) -#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n))) -#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0) -#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) -#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) -#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) -#define BB_PLL_ENA_SC0_REG REG(0x34C0) -#define BB_PLL8_STATUS_REG REG(0x3158) -#define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off))) -#define PLL8_STATUS_BIT 16 - -#define PLL_LOCK_DET_STATUS_REG REG(0x03420) -#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C) -#define CFPB_CLK_NS_REG REG(0x0264C) -#define CFPB0_HCLK_CTL_REG REG(0x02650) -#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0) -#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0) -#define EBI2_CLK_CTL_REG REG(0x03B00) - -#define USB30_MASTER_CLK_CTL_REG REG(0x3b24) -#define USB30_MASTER_CLK_MD REG(0x3b28) -#define USB30_MASTER_CLK_NS REG(0x3b2c) -#define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34) -#define USB30_MOC_UTMI_CLK_MD REG(0x3b40) -#define USB30_MOC_UTMI_CLK_NS REG(0x3b44) -#define USB30_MOC_UTMI_CLK_CTL REG(0x3b48) -#define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c) -#define USB30_RESET REG(0x3b50) - -#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8) - -#define CLK_BRANCH_ENA_MASK 0x00000010 -#define CLK_BRANCH_ENA_ENABLE 0x00000010 -#define CLK_BRANCH_ENA_DISABLE 0x00000000 -#define CLK_BRANCH_ENA(i) ((i) << 4) - -/* Register: CFPB_CLK_NS */ -#define CLK_DIV_MASK 0x00000003 -#define CLK_DIV_DIV_1 0x00000000 -#define CLK_DIV_DIV_2 0x00000001 -#define CLK_DIV_DIV_3 0x00000002 -#define CLK_DIV_DIV_4 0x00000003 -#define CLK_DIV(i) ((i) << 0) - -#define MN_MODE_DUAL_EDGE 0x2 -#define BIT_POS_31 31 -#define BIT_POS_16 16 -#define BIT_POS_6 6 -#define BIT_POS_0 0 -#define BIT_POS_15 15 - -#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l) -#define BVAL(m, l, val) (((val) << l) & BM(m, l)) - -/* MD Registers */ -#define MD4(m_lsb, m, n_lsb, n) \ - (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n))) - -#define MD8(m_lsb, m, n_lsb, n) \ - (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n))) - -/* NS Registers */ -#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(n_msb, n_lsb, ~(n-m)) \ - | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \ - | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) - -#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \ - | BVAL(s_msb, s_lsb, s)) - -#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \ - (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) - -#define NS_DIV(d_msb , d_lsb, d) \ - BVAL(d_msb, d_lsb, (d-1)) - -#define NS_SRC_SEL(s_msb, s_lsb, s) \ - BVAL(s_msb, s_lsb, s) - -#define GMAC_AHB_RESET 0x903E24 - -#define SRC_SEL_PLL0 (0x2 << 0) -#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) -#define MNCNTR_ENABLE (0x1 << 8) -#define MNCNTR_RST_ACTIVE (0x1 << 7) -#define N_VAL 15 - -#define GMAC_CORE_RESET(n) \ - ((void *)(0x903CBC + ((n) * 0x20))) - -#define GMACSEC_CORE_RESET(n) \ - ((void *)(0x903E28 + ((n - 1) * 4))) - -#define GMAC_COREn_CLCK_SRC_CTL(N) \ - (0x00900000 + (0x3CA0 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC0_MD(N) \ - (0x00900000 + (0x3CA4 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC1_MD(N) \ - (0x00900000 + (0x3CA8 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC0_NS(N) \ - (0x00900000 + (0x3CAC + (32*(N-1)))) - -#define GMAC_COREn_CLCK_SRC1_NS(N) \ - (0x00900000 + (0x3CB0 + (32*(N-1)))) - -#define DISABLE_DUAL_MN8_SEL (0) -#define DISABLE_CLK_LOW_PWR (0 << 2) -#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1) - -/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */ -#define GMAC_CORE_CLCK_M 0x32 -#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */ -#define GMAC_CORE_CLCK_M_SHIFT 16 -#define GMAC_CORE_CLCK_D_SHIFT 0 -#define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT) -#define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT) - -/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */ -#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */ -#define GMAC_CORE_CLCK_N_SHIFT 16 -#define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT) -#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */ -#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */ -#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */ -#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5 -#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */ -#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */ -#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3 -#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */ -#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */ -#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0 -#define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */ -#define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1)))) - -#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) -#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) - - -/* Uart specific clock settings */ - -void uart_pll_vote_clk_enable(unsigned int); -void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, - unsigned int d, unsigned int clk_dummy); -void nand_clock_config(void); -void usb_clock_config(void); - -#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/gpio.h b/src/soc/qualcomm/ipq806x/include/gpio.h deleted file mode 100644 index 276022c..0000000 --- a/src/soc/qualcomm/ipq806x/include/gpio.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* - Source : APQ8064 LK Boot - - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __SOC_QUALCOMM_IPQ806X_GPIO_H_ -#define __SOC_QUALCOMM_IPQ806X_GPIO_H_ - -#include <gpiolib.h> - -#define GPIO_FUNC_ENABLE 1 -#define GPIO_FUNC_DISABLE 0 -#define FUNC_SEL_1 1 -#define FUNC_SEL_3 3 -#define FUNC_SEL_GPIO 0 -#define GPIO_DRV_STR_10MA 0x4 -#define GPIO_DRV_STR_11MA 0x7 - -/* GPIO TLMM: Direction */ -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 - -/* GPIO TLMM: Pullup/Pulldown */ -#define GPIO_NO_PULL 0 -#define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 - -/* GPIO TLMM: Drive Strength */ -#define GPIO_2MA 0 -#define GPIO_4MA 1 -#define GPIO_6MA 2 -#define GPIO_8MA 3 -#define GPIO_10MA 4 -#define GPIO_12MA 5 -#define GPIO_14MA 6 -#define GPIO_16MA 7 - -/* GPIO TLMM: Status */ -#define GPIO_DISABLE 0 -#define GPIO_ENABLE 1 - -/* GPIO MAX Valid # */ -#define GPIO_MAX_NUM 68 - -/* GPIO TLMM: Mask */ -#define GPIO_CFG_PULL_MASK 0x3 -#define GPIO_CFG_FUNC_MASK 0xF -#define GPIO_CFG_DRV_MASK 0x7 -#define GPIO_CFG_OE_MASK 0x1 - -/* GPIO TLMM: Shift */ -#define GPIO_CFG_PULL_SHIFT 0 -#define GPIO_CFG_FUNC_SHIFT 2 -#define GPIO_CFG_DRV_SHIFT 6 -#define GPIO_CFG_OE_SHIFT 9 - -/* GPIO IO: Mask */ -#define GPIO_IO_IN_MASK 0x1 -#define GPIO_IO_OUT_MASK 0x1 - -/* GPIO IO: Shift */ -#define GPIO_IO_IN_SHIFT 0 -#define GPIO_IO_OUT_SHIFT 1 - -void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, - unsigned int pull, unsigned int drvstr, - unsigned int enable); - -void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, - unsigned int *pull, unsigned int *drvstr, - unsigned int *enable); - -void gpio_io_config_set(gpio_t gpio, unsigned int out); - -/* Keep this to maintain backwards compatibility with the vendor API. */ -static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func, - unsigned int dir, unsigned int pull, - unsigned int drvstr, unsigned int enable) -{ - gpio_tlmm_config_set(gpio, func, pull, drvstr, enable); -} -#endif // __SOC_QUALCOMM_IPQ806X_GPIO_H_ diff --git a/src/soc/qualcomm/ipq806x/include/gsbi.h b/src/soc/qualcomm/ipq806x/include/gsbi.h deleted file mode 100644 index c12d6fd..0000000 --- a/src/soc/qualcomm/ipq806x/include/gsbi.h +++ /dev/null @@ -1,35 +0,0 @@ -/* -* Copyright (c) 2004-2011 Atheros Communications Inc. -* Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. -* -* Permission to use, copy, modify, and/or distribute this software for any -* purpose with or without fee is hereby granted, provided that the above -* copyright notice and this permission notice appear in all copies. -* -* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -*/ - - -#ifndef __GSBI_H_ -#define __GSBI_H_ - -/* GSBI Registers */ -#define GSBI_CTRL_REG(base) ((base) + 0x0) - -#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4 -#define GSBI_PROTOCOL_CODE_I2C 0x2 -#define GSBI_PROTOCOL_CODE_SPI 0x3 -#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4 -#define GSBI_PROTOCOL_CODE_I2C_UART 0x6 - -#define GSBI_HCLK_CTL_S 4 -#define GSBI_HCLK_CTL_CLK_ENA 0x1 - -#endif - diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h deleted file mode 100644 index c9c8fc4..0000000 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * - * Copyright (c) 2008, Google Inc. - * All rights reserved. - * - * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_ -#define __SOC_QUALCOMM_IPQ806X_IOMAP_H_ - -#include <arch/io.h> -#include <cdp.h> - -/* Typecast to allow integers being passed as address - This needs to be included because vendor code is not compliant with our - macros for read/write. Hence, special macros for readl_i and writel_i are - included to do this in one place for all occurrences in vendor code - */ -#define readl_i(a) read32((const void *)(a)) -#define writel_i(v,a) write32(v,(void *)a) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) - -#define MSM_CLK_CTL_BASE 0x00900000 - -#define MSM_TMR_BASE 0x0200A000 -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) - -#define GPT_REG(off) ((void *)(MSM_GPT_BASE + (off))) -#define DGT_REG(off) (MSM_DGT_BASE + (off)) - -#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) -#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038) -#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C) -#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C) - -#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820) - -#define GPT_MATCH_VAL GPT_REG(0x0000) -#define GPT_COUNT_VAL GPT_REG(0x0004) -#define GPT_ENABLE GPT_REG(0x0008) -#define GPT_CLEAR GPT_REG(0x000C) - -#define GPT1_MATCH_VAL GPT_REG(0x00010) -#define GPT1_COUNT_VAL GPT_REG(0x00014) -#define GPT1_ENABLE GPT_REG(0x00018) -#define GPT1_CLEAR GPT_REG(0x0001C) - -#define DGT_MATCH_VAL DGT_REG(0x0000) -#define DGT_COUNT_VAL DGT_REG(0x0004) -#define DGT_ENABLE DGT_REG(0x0008) -#define DGT_CLEAR DGT_REG(0x000C) -#define DGT_CLK_CTL DGT_REG(0x0010) - -#define TLMM_BASE_ADDR ((char *)0x00800000) -#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) -#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) - -/* Yes, this is not a typo... host2 is actually mapped before host1. */ -#define USB_HOST2_XHCI_BASE 0x10000000 -#define USB_HOST2_DWC3_BASE 0x1000C100 -#define USB_HOST2_PHY_BASE 0x100F8800 -#define USB_HOST1_XHCI_BASE 0x11000000 -#define USB_HOST1_DWC3_BASE 0x1100C100 -#define USB_HOST1_PHY_BASE 0x110F8800 - -#define GSBI_1 1 -#define GSBI_2 2 -#define GSBI_4 4 -#define GSBI_2 2 -#define UART1_DM_BASE 0x12450000 -#define UART_GSBI1_BASE 0x12440000 -#define UART2_DM_BASE 0x12490000 -#define UART_GSBI2_BASE 0x12480000 -#define UART4_DM_BASE 0x16340000 -#define UART_GSBI4_BASE 0x16300000 - -#define UART2_DM_BASE 0x12490000 -#define UART_GSBI2_BASE 0x12480000 - -#endif // __SOC_QUALCOMM_IPQ806X_IOMAP_H_ diff --git a/src/soc/qualcomm/ipq806x/include/ipq_timer.h b/src/soc/qualcomm/ipq806x/include/ipq_timer.h deleted file mode 100644 index 4e1ef34..0000000 --- a/src/soc/qualcomm/ipq806x/include/ipq_timer.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google, Inc. nor the names of its contributors - * may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#define TIMER_LOAD_VAL 0x21 - -#define GPT_ENABLE_CLR_ON_MATCH_EN 2 -#define GPT_ENABLE_EN 1 -#define DGT_ENABLE_CLR_ON_MATCH_EN 2 -#define DGT_ENABLE_EN 1 - -#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) - - diff --git a/src/soc/qualcomm/ipq806x/include/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/ipq_uart.h deleted file mode 100644 index 90ca704..0000000 --- a/src/soc/qualcomm/ipq806x/include/ipq_uart.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2012 The Linux Foundation. All rights reserved.* - * - * Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * * Neither the name of Code Aurora Forum, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __UART_DM_H__ -#define __UART_DM_H__ - -#define PERIPH_BLK_BLSP 0 - -#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ - ((value << (32 - end_pos))\ - >> (32 - (end_pos - start_pos))) - -extern void __udelay(unsigned long usec); - - -enum MSM_BOOT_UART_DM_PARITY_MODE { - MSM_BOOT_UART_DM_NO_PARITY, - MSM_BOOT_UART_DM_ODD_PARITY, - MSM_BOOT_UART_DM_EVEN_PARITY, - MSM_BOOT_UART_DM_SPACE_PARITY -}; - -/* UART Stop Bit Length */ -enum MSM_BOOT_UART_DM_STOP_BIT_LEN { - MSM_BOOT_UART_DM_SBL_9_16, - MSM_BOOT_UART_DM_SBL_1, - MSM_BOOT_UART_DM_SBL_1_9_16, - MSM_BOOT_UART_DM_SBL_2 -}; - -/* UART Bits per Char */ -enum MSM_BOOT_UART_DM_BITS_PER_CHAR { - MSM_BOOT_UART_DM_5_BPS, - MSM_BOOT_UART_DM_6_BPS, - MSM_BOOT_UART_DM_7_BPS, - MSM_BOOT_UART_DM_8_BPS -}; - -/* 8-N-1 Configuration */ -#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ - (MSM_BOOT_UART_DM_SBL_1 << 2) | \ - (MSM_BOOT_UART_DM_8_BPS << 4)) - -/* UART_DM Registers */ - -/* UART Operational Mode Register */ -#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) -#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) -#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) -#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) - -/* UART Clock Selection Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) -#else -#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) -#endif - -/* UART DM TX FIFO Registers - 4 */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) -#else -#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) -#endif - -/* UART Command Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) -#else -#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) -#endif -#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) -#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) -#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) -#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) - -/* UART Channel Command */ -#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) -#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) -#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ - | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) -#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) -#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) -#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) -#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) -#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) -#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) -#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) -#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) -#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) -#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) -#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) -#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) -#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) -#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) -#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) -#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) -#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) -#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) - -/*UART General Command */ -#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) - -#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) -#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) -#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) -#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) -#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) -#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) - -/* UART Interrupt Mask Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) -#else -#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) -#endif - -#define MSM_BOOT_UART_DM_TXLEV (1 << 0) -#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) -#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) -#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) -#define MSM_BOOT_UART_DM_RXLEV (1 << 4) -#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) -#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) -#define MSM_BOOT_UART_DM_TX_READY (1 << 7) -#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) -#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) -#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) -#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) -#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) - -#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ - MSM_BOOT_UART_DM_TXLEV | \ - MSM_BOOT_UART_DM_RXSTALE) - -/* UART Interrupt Programming Register */ -#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f -#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ - -/* UART Transmit/Receive FIFO Watermark Register */ -#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) -/* Interrupt is generated when FIFO level is less than or equal to this value */ -#define MSM_BOOT_UART_DM_TFW_VALUE 0 - -#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) -/*Interrupt generated when no of words in RX FIFO is greater than this value */ -#define MSM_BOOT_UART_DM_RFW_VALUE 0 - -/* UART Hunt Character Register */ -#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) - -/* Used for RX transfer initialization */ -#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) - -/* Default DMRX value - any value bigger than FIFO size would be fine */ -#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 - -/* Register to enable IRDA function */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) -#else -#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) -#endif - -/* UART Data Mover Enable Register */ -#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) - -/* Number of characters for Transmission */ -#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) - -/* UART RX FIFO Base Address */ -#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) - -/* UART Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) -#else -#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) -#endif -#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) -#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) -#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) -#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) -#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) -#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) -#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) -#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) -#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) - -/* UART Receive FIFO Registers - 4 in numbers */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) -#else -#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) -#endif - -/* UART Masked Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) -#else -#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) -#endif - -/* UART Interrupt Status Register */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) -#else -#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) -#endif - -/* Number of characters received since the end of last RX transfer */ -#if PERIPH_BLK_BLSP -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) -#else -#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) -#endif - -/* UART TX FIFO Status Register */ -#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) -#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* UART RX FIFO Status Register */ -#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) -#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) -#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) -#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) -#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) - -/* Macros for Common Errors */ -#define MSM_BOOT_UART_DM_E_SUCCESS 0 -#define MSM_BOOT_UART_DM_E_FAILURE 1 -#define MSM_BOOT_UART_DM_E_TIMEOUT 2 -#define MSM_BOOT_UART_DM_E_INVAL 3 -#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 -#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 - -#endif /* __UART_DM_H__ */ - diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h new file mode 100644 index 0000000..c7de23f --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h @@ -0,0 +1,139 @@ +/* * Copyright (c) 2012 The Linux Foundation. All rights reserved.* */ + + +#ifndef _IPQ806X_CDP_H_ +#define _IPQ806X_CDP_H_ + +#include <types.h> + +unsigned smem_get_board_machtype(void); + +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; + +typedef struct { + unsigned int gpio; + unsigned int func; + unsigned int dir; + unsigned int pull; + unsigned int drvstr; + unsigned int enable; +} gpio_func_data_t; + +typedef struct { + unsigned int m_value; + unsigned int n_value; + unsigned int d_value; +} uart_clk_mnd_t; + +/* SPI Mode */ + +typedef enum { + NOR_SPI_MODE_0, + NOR_SPI_MODE_1, + NOR_SPI_MODE_2, + NOR_SPI_MODE_3, +} spi_mode; + +/* SPI GSBI Bus number */ + +typedef enum { + GSBI_BUS_5 = 0, + GSBI_BUS_6, + GSBI_BUS_7, +} spi_gsbi_bus_num; + +/* SPI Chip selects */ + +typedef enum { + SPI_CS_0 , + SPI_CS_1, + SPI_CS_2, + SPI_CS_3, +} spi_cs; + +/* Flash Types */ + +typedef enum { + ONLY_NAND, + ONLY_NOR, + NAND_NOR, + NOR_MMC, +} flash_desc; + +#define NO_OF_DBG_UART_GPIOS 2 + +#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 +#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 + +/* SPI parameters */ + +typedef struct { + spi_mode mode; + spi_gsbi_bus_num bus_number; + spi_cs chip_select; + int vendor; +} spinorflash_params_t; + +typedef struct { + unsigned count; + uint8_t addr[7]; +} ipq_gmac_phy_addr_t; + +typedef struct { + unsigned base; + int unit; + unsigned is_macsec; + unsigned mac_pwr0; + unsigned mac_pwr1; + unsigned mac_conn_to_phy; + phy_interface_t phy; + ipq_gmac_phy_addr_t phy_addr; +} ipq_gmac_board_cfg_t; + +#define IPQ_GMAC_NMACS 4 + +/* Board specific parameters */ +typedef struct { +#if 0 + unsigned int gmac_gpio_count; + gpio_func_data_t *gmac_gpio; + ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS]; + flash_desc flashdesc; + spinorflash_params_t flash_param; +#endif +} __attribute__ ((__packed__)) board_ipq806x_params_t; + +extern board_ipq806x_params_t *gboard_param; + +#if 0 +static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg) +{ + /* + * 'cfg' is valid if and only if + * unit number is non-negative and less than IPQ_GMAC_NMACS. + * 'cfg' pointer lies within the array range of + * board_ipq806x_params_t->gmac_cfg[] + */ + return ((cfg >= &gboard_param->gmac_cfg[0]) && + (cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) && + (cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS)); +} +#endif + +unsigned int get_board_index(unsigned machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); +#endif diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h new file mode 100644 index 0000000..837b831 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK Boot + * + * Copyright (c) 2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IPQ860X_CLOCK_H_ +#define __IPQ860X_CLOCK_H_ + +#include <soc/iomap.h> + +/* UART clock @ 7.3728 MHz */ +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC + +/* UART specific definitions */ + +#define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) +#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) +#define Uart_mnd_en_mask BIT(8) * !!(625) +#define Uart_en_mask BIT(11) +#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n))) +#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0) +#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) +#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) +#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) +#define BB_PLL_ENA_SC0_REG REG(0x34C0) +#define BB_PLL8_STATUS_REG REG(0x3158) +#define REG(off) ((void *)(MSM_CLK_CTL_BASE + (off))) +#define PLL8_STATUS_BIT 16 + +#define PLL_LOCK_DET_STATUS_REG REG(0x03420) +#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C) +#define CFPB_CLK_NS_REG REG(0x0264C) +#define CFPB0_HCLK_CTL_REG REG(0x02650) +#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0) +#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0) +#define EBI2_CLK_CTL_REG REG(0x03B00) + +#define USB30_MASTER_CLK_CTL_REG REG(0x3b24) +#define USB30_MASTER_CLK_MD REG(0x3b28) +#define USB30_MASTER_CLK_NS REG(0x3b2c) +#define USB30_1_MASTER_CLK_CTL_REG REG(0x3b34) +#define USB30_MOC_UTMI_CLK_MD REG(0x3b40) +#define USB30_MOC_UTMI_CLK_NS REG(0x3b44) +#define USB30_MOC_UTMI_CLK_CTL REG(0x3b48) +#define USB30_1_MOC_UTMI_CLK_CTL REG(0x3b4c) +#define USB30_RESET REG(0x3b50) + +#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8) + +#define CLK_BRANCH_ENA_MASK 0x00000010 +#define CLK_BRANCH_ENA_ENABLE 0x00000010 +#define CLK_BRANCH_ENA_DISABLE 0x00000000 +#define CLK_BRANCH_ENA(i) ((i) << 4) + +/* Register: CFPB_CLK_NS */ +#define CLK_DIV_MASK 0x00000003 +#define CLK_DIV_DIV_1 0x00000000 +#define CLK_DIV_DIV_2 0x00000001 +#define CLK_DIV_DIV_3 0x00000002 +#define CLK_DIV_DIV_4 0x00000003 +#define CLK_DIV(i) ((i) << 0) + +#define MN_MODE_DUAL_EDGE 0x2 +#define BIT_POS_31 31 +#define BIT_POS_16 16 +#define BIT_POS_6 6 +#define BIT_POS_0 0 +#define BIT_POS_15 15 + +#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l) +#define BVAL(m, l, val) (((val) << l) & BM(m, l)) + +/* MD Registers */ +#define MD4(m_lsb, m, n_lsb, n) \ + (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n))) + +#define MD8(m_lsb, m, n_lsb, n) \ + (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n))) + +/* NS Registers */ +#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(n_msb, n_lsb, ~(n-m)) \ + | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \ + | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) + +#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \ + | BVAL(s_msb, s_lsb, s)) + +#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \ + (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s)) + +#define NS_DIV(d_msb , d_lsb, d) \ + BVAL(d_msb, d_lsb, (d-1)) + +#define NS_SRC_SEL(s_msb, s_lsb, s) \ + BVAL(s_msb, s_lsb, s) + +#define GMAC_AHB_RESET 0x903E24 + +#define SRC_SEL_PLL0 (0x2 << 0) +#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) +#define MNCNTR_ENABLE (0x1 << 8) +#define MNCNTR_RST_ACTIVE (0x1 << 7) +#define N_VAL 15 + +#define GMAC_CORE_RESET(n) \ + ((void *)(0x903CBC + ((n) * 0x20))) + +#define GMACSEC_CORE_RESET(n) \ + ((void *)(0x903E28 + ((n - 1) * 4))) + +#define GMAC_COREn_CLCK_SRC_CTL(N) \ + (0x00900000 + (0x3CA0 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC0_MD(N) \ + (0x00900000 + (0x3CA4 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC1_MD(N) \ + (0x00900000 + (0x3CA8 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC0_NS(N) \ + (0x00900000 + (0x3CAC + (32*(N-1)))) + +#define GMAC_COREn_CLCK_SRC1_NS(N) \ + (0x00900000 + (0x3CB0 + (32*(N-1)))) + +#define DISABLE_DUAL_MN8_SEL (0) +#define DISABLE_CLK_LOW_PWR (0 << 2) +#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1) + +/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */ +#define GMAC_CORE_CLCK_M 0x32 +#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */ +#define GMAC_CORE_CLCK_M_SHIFT 16 +#define GMAC_CORE_CLCK_D_SHIFT 0 +#define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT) +#define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT) + +/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */ +#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */ +#define GMAC_CORE_CLCK_N_SHIFT 16 +#define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT) +#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */ +#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */ +#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */ +#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5 +#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */ +#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */ +#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3 +#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */ +#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */ +#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0 +#define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */ +#define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1)))) + +#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) +#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) + + +/* Uart specific clock settings */ + +void uart_pll_vote_clk_enable(unsigned int); +void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n, + unsigned int d, unsigned int clk_dummy); +void nand_clock_config(void); +void usb_clock_config(void); + +#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/gpio.h b/src/soc/qualcomm/ipq806x/include/soc/gpio.h new file mode 100644 index 0000000..276022c --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/gpio.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + Source : APQ8064 LK Boot + + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_IPQ806X_GPIO_H_ +#define __SOC_QUALCOMM_IPQ806X_GPIO_H_ + +#include <gpiolib.h> + +#define GPIO_FUNC_ENABLE 1 +#define GPIO_FUNC_DISABLE 0 +#define FUNC_SEL_1 1 +#define FUNC_SEL_3 3 +#define FUNC_SEL_GPIO 0 +#define GPIO_DRV_STR_10MA 0x4 +#define GPIO_DRV_STR_11MA 0x7 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +/* GPIO MAX Valid # */ +#define GPIO_MAX_NUM 68 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_MASK 0x3 +#define GPIO_CFG_FUNC_MASK 0xF +#define GPIO_CFG_DRV_MASK 0x7 +#define GPIO_CFG_OE_MASK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHIFT 0 +#define GPIO_CFG_FUNC_SHIFT 2 +#define GPIO_CFG_DRV_SHIFT 6 +#define GPIO_CFG_OE_SHIFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_MASK 0x1 +#define GPIO_IO_OUT_MASK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHIFT 0 +#define GPIO_IO_OUT_SHIFT 1 + +void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, + unsigned int pull, unsigned int drvstr, + unsigned int enable); + +void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, + unsigned int *pull, unsigned int *drvstr, + unsigned int *enable); + +void gpio_io_config_set(gpio_t gpio, unsigned int out); + +/* Keep this to maintain backwards compatibility with the vendor API. */ +static inline void gpio_tlmm_config(unsigned int gpio, unsigned int func, + unsigned int dir, unsigned int pull, + unsigned int drvstr, unsigned int enable) +{ + gpio_tlmm_config_set(gpio, func, pull, drvstr, enable); +} +#endif // __SOC_QUALCOMM_IPQ806X_GPIO_H_ diff --git a/src/soc/qualcomm/ipq806x/include/soc/gsbi.h b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h new file mode 100644 index 0000000..c12d6fd --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2004-2011 Atheros Communications Inc. +* Copyright (c) 2011-2012 The Linux Foundation. All rights reserved. +* +* Permission to use, copy, modify, and/or distribute this software for any +* purpose with or without fee is hereby granted, provided that the above +* copyright notice and this permission notice appear in all copies. +* +* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +*/ + + +#ifndef __GSBI_H_ +#define __GSBI_H_ + +/* GSBI Registers */ +#define GSBI_CTRL_REG(base) ((base) + 0x0) + +#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4 +#define GSBI_PROTOCOL_CODE_I2C 0x2 +#define GSBI_PROTOCOL_CODE_SPI 0x3 +#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4 +#define GSBI_PROTOCOL_CODE_I2C_UART 0x6 + +#define GSBI_HCLK_CTL_S 4 +#define GSBI_HCLK_CTL_CLK_ENA 0x1 + +#endif + diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h new file mode 100644 index 0000000..ad7056e --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. + * + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_ +#define __SOC_QUALCOMM_IPQ806X_IOMAP_H_ + +#include <arch/io.h> +#include <soc/cdp.h> + +/* Typecast to allow integers being passed as address + This needs to be included because vendor code is not compliant with our + macros for read/write. Hence, special macros for readl_i and writel_i are + included to do this in one place for all occurrences in vendor code + */ +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v,a) write32(v,(void *)a) +#define clrsetbits_le32_i(addr, clear, set) \ + clrsetbits_le32(((void *)(addr)), (clear), (set)) + +#define MSM_CLK_CTL_BASE 0x00900000 + +#define MSM_TMR_BASE 0x0200A000 +#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) + +#define GPT_REG(off) ((void *)(MSM_GPT_BASE + (off))) +#define DGT_REG(off) (MSM_DGT_BASE + (off)) + +#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) +#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038) +#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C) +#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C) + +#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820) + +#define GPT_MATCH_VAL GPT_REG(0x0000) +#define GPT_COUNT_VAL GPT_REG(0x0004) +#define GPT_ENABLE GPT_REG(0x0008) +#define GPT_CLEAR GPT_REG(0x000C) + +#define GPT1_MATCH_VAL GPT_REG(0x00010) +#define GPT1_COUNT_VAL GPT_REG(0x00014) +#define GPT1_ENABLE GPT_REG(0x00018) +#define GPT1_CLEAR GPT_REG(0x0001C) + +#define DGT_MATCH_VAL DGT_REG(0x0000) +#define DGT_COUNT_VAL DGT_REG(0x0004) +#define DGT_ENABLE DGT_REG(0x0008) +#define DGT_CLEAR DGT_REG(0x000C) +#define DGT_CLK_CTL DGT_REG(0x0010) + +#define TLMM_BASE_ADDR ((char *)0x00800000) +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) +#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) + +/* Yes, this is not a typo... host2 is actually mapped before host1. */ +#define USB_HOST2_XHCI_BASE 0x10000000 +#define USB_HOST2_DWC3_BASE 0x1000C100 +#define USB_HOST2_PHY_BASE 0x100F8800 +#define USB_HOST1_XHCI_BASE 0x11000000 +#define USB_HOST1_DWC3_BASE 0x1100C100 +#define USB_HOST1_PHY_BASE 0x110F8800 + +#define GSBI_1 1 +#define GSBI_2 2 +#define GSBI_4 4 +#define GSBI_2 2 +#define UART1_DM_BASE 0x12450000 +#define UART_GSBI1_BASE 0x12440000 +#define UART2_DM_BASE 0x12490000 +#define UART_GSBI2_BASE 0x12480000 +#define UART4_DM_BASE 0x16340000 +#define UART_GSBI4_BASE 0x16300000 + +#define UART2_DM_BASE 0x12490000 +#define UART_GSBI2_BASE 0x12480000 + +#endif // __SOC_QUALCOMM_IPQ806X_IOMAP_H_ diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h new file mode 100644 index 0000000..4e1ef34 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define TIMER_LOAD_VAL 0x21 + +#define GPT_ENABLE_CLR_ON_MATCH_EN 2 +#define GPT_ENABLE_EN 1 +#define DGT_ENABLE_CLR_ON_MATCH_EN 2 +#define DGT_ENABLE_EN 1 + +#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) + + diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h new file mode 100644 index 0000000..90ca704 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2012 The Linux Foundation. All rights reserved.* + * + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#define PERIPH_BLK_BLSP 0 + +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos))\ + >> (32 - (end_pos - start_pos))) + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ + | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +#endif /* __UART_DM_H__ */ + diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld new file mode 100644 index 0000000..3059603 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* TODO: This should be revised by someone who understands the SoC better. */ + +SECTIONS +{ + /* TODO: add SRAM_START(), SRAM_END() and REGION(reserved_sbl) */ + TTB(0x2A05C000, 48K) + + DRAM_START(0x40000000) + CBFS_CACHE(0x405CC000, 192K) + STACK(0x405FC000, 16K) + /* TODO: "256K bytes left for TZBSP"... what does that mean? */ + BOOTBLOCK(0x40600000, 32K) + PRERAM_CBMEM_CONSOLE(0x40618000, 8K) + ROMSTAGE(0x40620000, 128K) + RAMSTAGE(0x40640000, 128K) + DMA_COHERENT(0x5A000000, 2M) +} diff --git a/src/soc/qualcomm/ipq806x/include/soc/spi.h b/src/soc/qualcomm/ipq806x/include/soc/spi.h new file mode 100644 index 0000000..f7dda07 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/spi.h @@ -0,0 +1,282 @@ +/* + * Register definitions for the IPQ GSBI Controller + * Copyright (c) 2012 The Linux Foundation. All rights reserved. + */ + +#ifndef _IPQ806X_SPI_H_ +#define _IPQ806X_SPI_H_ + +#include <spi_flash.h> + +#define QUP5_BASE 0x1a280000 +#define QUP6_BASE 0x16580000 +#define QUP7_BASE 0x16680000 + +#define GSBI5_BASE 0x1a200000 +#define GSBI6_BASE 0x16500000 +#define GSBI7_BASE 0x16600000 + +#define GSBI5_QUP5_REG_BASE (QUP5_BASE + 0x00000000) +#define GSBI6_QUP6_REG_BASE (QUP6_BASE + 0x00000000) +#define GSBI7_QUP7_REG_BASE (QUP7_BASE + 0x00000000) + +#define GSBI5_REG_BASE (GSBI5_BASE + 0x00000000) +#define GSBI6_REG_BASE (GSBI6_BASE + 0x00000000) +#define GSBI7_REG_BASE (GSBI7_BASE + 0x00000000) + +#define BOOT_SPI_PORT5_BASE QUP5_BASE +#define BOOT_SPI_PORT6_BASE QUP6_BASE +#define BOOT_SPI_PORT7_BASE QUP7_BASE + +#define GSBI5_SPI_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000300) +#define GSBI6_SPI_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000300) +#define GSBI7_SPI_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000300) + +#define GSBI5_SPI_IO_CONTROL_REG (GSBI5_QUP5_REG_BASE + 0x00000304) +#define GSBI6_SPI_IO_CONTROL_REG (GSBI6_QUP6_REG_BASE + 0x00000304) +#define GSBI7_SPI_IO_CONTROL_REG (GSBI7_QUP7_REG_BASE + 0x00000304) + +#define GSBI5_SPI_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x00000308) +#define GSBI6_SPI_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x00000308) +#define GSBI7_SPI_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x00000308) + +#define GSBI5_SPI_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x0000030c) +#define GSBI6_SPI_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x0000030c) +#define GSBI7_SPI_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x0000030c) + +#define GSBI5_GSBI_CTRL_REG_REG (GSBI5_REG_BASE + 0x00000000) +#define GSBI6_GSBI_CTRL_REG_REG (GSBI6_REG_BASE + 0x00000000) +#define GSBI7_GSBI_CTRL_REG_REG (GSBI7_REG_BASE + 0x00000000) + +#define GSBI5_QUP_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000000) +#define GSBI6_QUP_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000000) +#define GSBI7_QUP_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000000) + +#define GSBI5_QUP_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x0000001c) +#define GSBI6_QUP_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x0000001c) +#define GSBI7_QUP_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x0000001c) + +#define GSBI5_QUP_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x00000020) +#define GSBI6_QUP_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x00000020) +#define GSBI7_QUP_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x00000020) + +#define GSBI5_QUP_OPERATIONAL_REG (GSBI5_QUP5_REG_BASE + 0x00000018) +#define GSBI6_QUP_OPERATIONAL_REG (GSBI6_QUP6_REG_BASE + 0x00000018) +#define GSBI7_QUP_OPERATIONAL_REG (GSBI7_QUP7_REG_BASE + 0x00000018) + +#define GSBI5_QUP_IO_MODES_REG (GSBI5_QUP5_REG_BASE + 0x00000008) +#define GSBI6_QUP_IO_MODES_REG (GSBI6_QUP6_REG_BASE + 0x00000008) +#define GSBI7_QUP_IO_MODES_REG (GSBI7_QUP7_REG_BASE + 0x00000008) + +#define GSBI5_QUP_STATE_REG (GSBI5_QUP5_REG_BASE + 0x00000004) +#define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004) +#define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004) + +#define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x0000010c) +#define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x0000010c) +#define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x0000010c) + +#define GSBI5_QUP_IN_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x00000214) +#define GSBI6_QUP_IN_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x00000214) +#define GSBI7_QUP_IN_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x00000214) + +#define GSBI5_QUP_INPUT_FIFOc_REG(c) \ + (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c)) +#define GSBI6_QUP_INPUT_FIFOc_REG(c) \ + (GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c)) +#define GSBI7_QUP_INPUT_FIFOc_REG(c) \ + (GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c)) + +#define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c)) +#define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c)) +#define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \ + (GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c)) + +#define GSBI5_QUP_MX_INPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000200) +#define GSBI6_QUP_MX_INPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000200) +#define GSBI7_QUP_MX_INPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000200) + +#define GSBI5_QUP_MX_OUTPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000100) +#define GSBI6_QUP_MX_OUTPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000100) +#define GSBI7_QUP_MX_OUTPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000100) + +#define GSBI5_QUP_SW_RESET_REG (GSBI5_QUP5_REG_BASE + 0x0000000c) +#define GSBI6_QUP_SW_RESET_REG (GSBI6_QUP6_REG_BASE + 0x0000000c) +#define GSBI7_QUP_SW_RESET_REG (GSBI7_QUP7_REG_BASE + 0x0000000c) + +#define CLK_CTL_REG_BASE 0x00900000 +#define GSBIn_RESET_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029dc + 32 * ((n)-1)) + +#define SFAB_AHB_S3_FCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x0000216c) +#define CFPB_CLK_NS_REG \ + (CLK_CTL_REG_BASE + 0x0000264c) +#define SFAB_CFPB_S_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x000026c0) +#define CFPB_SPLITTER_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x000026e0) +#define CFPB0_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x00002650) +#define CFPB2_HCLK_CTL_REG \ + (CLK_CTL_REG_BASE + 0x00002658) +#define GSBIn_HCLK_CTL_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029c0 + 32 * ((n)-1)) +#define GSBIn_QUP_APPS_NS_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029cc + 32 * ((n)-1)) +#define GSBIn_QUP_APPS_MD_REG(n) \ + (CLK_CTL_REG_BASE + 0x000029c8 + 32 * ((n)-1)) +#define CLK_HALT_CFPB_STATEB_REG \ + (CLK_CTL_REG_BASE + 0x00002fd0) + +#define GSBI5_HCLK 23 +#define GSBI6_HCLK 19 +#define GSBI7_HCLK 15 +#define GSBI5_QUP_APPS_CLK 20 +#define GSBI6_QUP_APPS_CLK 16 +#define GSBI7_QUP_APPS_CLK 12 +#define GSBI_CLK_BRANCH_ENA_MSK (1 << 4) +#define GSBI_CLK_BRANCH_ENA (1 << 4) +#define GSBI_CLK_BRANCH_DIS (0 << 4) +#define QUP_CLK_BRANCH_ENA_MSK (1 << 9) +#define QUP_CLK_BRANCH_ENA (1 << 9) +#define QUP_CLK_BRANCH_DIS (0 << 9) +#define CLK_ROOT_ENA_MSK (1 << 11) +#define CLK_ROOT_ENA (1 << 11) +#define CLK_ROOT_DIS (0 << 11) + +#define QUP_STATE_VALID_BIT 2 +#define QUP_STATE_VALID 1 +#define QUP_STATE_MASK 0x3 +#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) +#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) +#define SPI_QUP_CONF_INPUT_MSK (1 << 7) +#define SPI_QUP_CONF_INPUT_ENA (0 << 7) +#define SPI_QUP_CONF_NO_INPUT (1 << 7) +#define SPI_QUP_CONF_OUTPUT_MSK (1 << 6) +#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) +#define SPI_QUP_CONF_NO_OUTPUT (1 << 6) +#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) +#define QUP_STATE_RESET_STATE 0x0 +#define QUP_STATE_RUN_STATE 0x1 +#define QUP_STATE_PAUSE_STATE 0x3 +#define SPI_BIT_WORD_MSK 0x1F +#define SPI_8_BIT_WORD 0x07 +#define PROTOCOL_CODE_MSK (0x07 << 4) +#define PROTOCOL_CODE_SPI (0x03 << 4) +#define LOOP_BACK_MSK (1 << 8) +#define NO_LOOP_BACK (0 << 8) +#define SLAVE_OPERATION_MSK (1 << 5) +#define SLAVE_OPERATION (0 << 5) +#define CLK_ALWAYS_ON (0 << 9) +#define MX_CS_MODE (0 << 8) +#define NO_TRI_STATE (1 << 0) +#define OUTPUT_BIT_SHIFT_MSK (1 << 16) +#define OUTPUT_BIT_SHIFT_EN (1 << 16) +#define INPUT_BLOCK_MODE_MSK (0x03 << 12) +#define INPUT_BLOCK_MODE (0x01 << 12) +#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10) +#define OUTPUT_BLOCK_MODE (0x01 << 10) +#define GSBI1_RESET (1 << 0) +#define GSBI1_RESET_MSK 0x1 + +#define GSBI_M_VAL_SHFT 16 +#define GSBIn_M_VAL_MSK (0xFF << GSBI_M_VAL_SHFT) +#define GSBI_N_VAL_SHFT 16 +#define GSBIn_N_VAL_MSK (0xFF << GSBI_N_VAL_SHFT) +#define GSBI_D_VAL_SHFT 0 +#define GSBIn_D_VAL_MSK (0xFF << GSBI_D_VAL_SHFT) +#define MNCNTR_RST_MSK (1 << 7) +#define MNCNTR_RST_ENA (1 << 7) +#define MNCNTR_RST_DIS (0 << 7) +#define MNCNTR_MSK (1 << 8) +#define MNCNTR_EN (1 << 8) +#define MNCNTR_DIS (0 << 8) +#define MNCNTR_MODE_MSK (0x3 << 5) +#define MNCNTR_MODE_BYPASS (0 << 5) +#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) +#define GSBI_PRE_DIV_SEL_SHFT 3 +#define GSBIn_PRE_DIV_SEL_MSK (0x3 << GSBI_PRE_DIV_SEL_SHFT) +#define GSBIn_PLL_SRC_MSK (0x03 << 0) +#define GSBIn_PLL_SRC_PXO (0 << 0) +#define GSBIn_PLL_SRC_PLL8 (0x3 << 0) + +#define SPI_INPUT_FIRST_MODE (1 << 9) +#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10) +#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5) +#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4) +#define OUTPUT_SERVICE_FLAG (1 << 8) +#define INPUT_SERVICE_FLAG (1 << 9) +#define QUP_OUTPUT_FIFO_FULL (1 << 6) +#define QUP_INPUT_FIFO_NOT_EMPTY (1 << 5) +#define SPI_INPUT_BLOCK_SIZE 4 +#define SPI_OUTPUT_BLOCK_SIZE 4 +#define GSBI5_SPI_CLK 21 +#define GSBI5_SPI_MISO 19 +#define GSBI5_SPI_MOSI 18 +#define GSBI5_SPI_CS_0 20 +#define GSBI5_SPI_CS_1 61 +#define GSBI5_SPI_CS_2 62 +#define GSBI5_SPI_CS_3 2 +#define GSBI6_SPI_CLK 30 +#define GSBI6_SPI_CS_0 29 +#define GSBI6_SPI_MISO 28 +#define GSBI6_SPI_MOSI 27 +#define GSBI7_SPI_CLK 9 +#define GSBI7_SPI_CS_0 8 +#define GSBI7_SPI_MISO 7 +#define GSBI7_SPI_MOSI 6 + +#define MSM_GSBI_MAX_FREQ 51200000 + +#define SPI_RESET_STATE 0 +#define SPI_RUN_STATE 1 +#define SPI_PAUSE_STATE 3 +#define SPI_CORE_RESET 0 +#define SPI_CORE_RUNNING 1 +#define GSBI_SPI_MODE_0 0 +#define GSBI_SPI_MODE_1 1 +#define GSBI_SPI_MODE_2 2 +#define GSBI_SPI_MODE_3 3 +#define GSBI5_SPI 0 +#define GSBI6_SPI 1 +#define GSBI7_SPI 2 + +struct gsbi_spi { + unsigned int spi_config; + unsigned int io_control; + unsigned int error_flags; + unsigned int error_flags_en; + unsigned int gsbi_ctrl; + unsigned int qup_config; + unsigned int qup_error_flags; + unsigned int qup_error_flags_en; + unsigned int qup_operational; + unsigned int qup_io_modes; + unsigned int qup_state; + unsigned int qup_input_fifo; + unsigned int qup_output_fifo; + unsigned int qup_mx_input_count; + unsigned int qup_mx_output_count; + unsigned int qup_sw_reset; + unsigned int qup_ns_reg; + unsigned int qup_md_reg; +}; + +struct ipq_spi_slave { + struct spi_slave slave; + const struct gsbi_spi *regs; + unsigned int mode; + unsigned int initialized; + unsigned long freq; + int allocated; +}; + +static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ipq_spi_slave, slave); +} + +#endif /* _IPQ_SPI_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/soc/usb.h b/src/soc/qualcomm/ipq806x/include/soc/usb.h new file mode 100644 index 0000000..c3c4c48 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/include/soc/usb.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _IPQ806X_USB_H_ +#define _IPQ806X_USB_H_ + +void setup_usb_host1(void); +void setup_usb_host2(void); + +#endif /* _IPQ806X_USB_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/spi.h b/src/soc/qualcomm/ipq806x/include/spi.h deleted file mode 100644 index f7dda07..0000000 --- a/src/soc/qualcomm/ipq806x/include/spi.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Register definitions for the IPQ GSBI Controller - * Copyright (c) 2012 The Linux Foundation. All rights reserved. - */ - -#ifndef _IPQ806X_SPI_H_ -#define _IPQ806X_SPI_H_ - -#include <spi_flash.h> - -#define QUP5_BASE 0x1a280000 -#define QUP6_BASE 0x16580000 -#define QUP7_BASE 0x16680000 - -#define GSBI5_BASE 0x1a200000 -#define GSBI6_BASE 0x16500000 -#define GSBI7_BASE 0x16600000 - -#define GSBI5_QUP5_REG_BASE (QUP5_BASE + 0x00000000) -#define GSBI6_QUP6_REG_BASE (QUP6_BASE + 0x00000000) -#define GSBI7_QUP7_REG_BASE (QUP7_BASE + 0x00000000) - -#define GSBI5_REG_BASE (GSBI5_BASE + 0x00000000) -#define GSBI6_REG_BASE (GSBI6_BASE + 0x00000000) -#define GSBI7_REG_BASE (GSBI7_BASE + 0x00000000) - -#define BOOT_SPI_PORT5_BASE QUP5_BASE -#define BOOT_SPI_PORT6_BASE QUP6_BASE -#define BOOT_SPI_PORT7_BASE QUP7_BASE - -#define GSBI5_SPI_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000300) -#define GSBI6_SPI_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000300) -#define GSBI7_SPI_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000300) - -#define GSBI5_SPI_IO_CONTROL_REG (GSBI5_QUP5_REG_BASE + 0x00000304) -#define GSBI6_SPI_IO_CONTROL_REG (GSBI6_QUP6_REG_BASE + 0x00000304) -#define GSBI7_SPI_IO_CONTROL_REG (GSBI7_QUP7_REG_BASE + 0x00000304) - -#define GSBI5_SPI_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x00000308) -#define GSBI6_SPI_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x00000308) -#define GSBI7_SPI_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x00000308) - -#define GSBI5_SPI_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x0000030c) -#define GSBI6_SPI_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x0000030c) -#define GSBI7_SPI_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x0000030c) - -#define GSBI5_GSBI_CTRL_REG_REG (GSBI5_REG_BASE + 0x00000000) -#define GSBI6_GSBI_CTRL_REG_REG (GSBI6_REG_BASE + 0x00000000) -#define GSBI7_GSBI_CTRL_REG_REG (GSBI7_REG_BASE + 0x00000000) - -#define GSBI5_QUP_CONFIG_REG (GSBI5_QUP5_REG_BASE + 0x00000000) -#define GSBI6_QUP_CONFIG_REG (GSBI6_QUP6_REG_BASE + 0x00000000) -#define GSBI7_QUP_CONFIG_REG (GSBI7_QUP7_REG_BASE + 0x00000000) - -#define GSBI5_QUP_ERROR_FLAGS_REG (GSBI5_QUP5_REG_BASE + 0x0000001c) -#define GSBI6_QUP_ERROR_FLAGS_REG (GSBI6_QUP6_REG_BASE + 0x0000001c) -#define GSBI7_QUP_ERROR_FLAGS_REG (GSBI7_QUP7_REG_BASE + 0x0000001c) - -#define GSBI5_QUP_ERROR_FLAGS_EN_REG (GSBI5_QUP5_REG_BASE + 0x00000020) -#define GSBI6_QUP_ERROR_FLAGS_EN_REG (GSBI6_QUP6_REG_BASE + 0x00000020) -#define GSBI7_QUP_ERROR_FLAGS_EN_REG (GSBI7_QUP7_REG_BASE + 0x00000020) - -#define GSBI5_QUP_OPERATIONAL_REG (GSBI5_QUP5_REG_BASE + 0x00000018) -#define GSBI6_QUP_OPERATIONAL_REG (GSBI6_QUP6_REG_BASE + 0x00000018) -#define GSBI7_QUP_OPERATIONAL_REG (GSBI7_QUP7_REG_BASE + 0x00000018) - -#define GSBI5_QUP_IO_MODES_REG (GSBI5_QUP5_REG_BASE + 0x00000008) -#define GSBI6_QUP_IO_MODES_REG (GSBI6_QUP6_REG_BASE + 0x00000008) -#define GSBI7_QUP_IO_MODES_REG (GSBI7_QUP7_REG_BASE + 0x00000008) - -#define GSBI5_QUP_STATE_REG (GSBI5_QUP5_REG_BASE + 0x00000004) -#define GSBI6_QUP_STATE_REG (GSBI6_QUP6_REG_BASE + 0x00000004) -#define GSBI7_QUP_STATE_REG (GSBI7_QUP7_REG_BASE + 0x00000004) - -#define GSBI5_QUP_OUT_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x0000010c) -#define GSBI6_QUP_OUT_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x0000010c) -#define GSBI7_QUP_OUT_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x0000010c) - -#define GSBI5_QUP_IN_FIFO_WORD_CNT_REG (GSBI5_QUP5_REG_BASE + 0x00000214) -#define GSBI6_QUP_IN_FIFO_WORD_CNT_REG (GSBI6_QUP6_REG_BASE + 0x00000214) -#define GSBI7_QUP_IN_FIFO_WORD_CNT_REG (GSBI7_QUP7_REG_BASE + 0x00000214) - -#define GSBI5_QUP_INPUT_FIFOc_REG(c) \ - (GSBI5_QUP5_REG_BASE + 0x00000218 + 4 * (c)) -#define GSBI6_QUP_INPUT_FIFOc_REG(c) \ - (GSBI6_QUP6_REG_BASE + 0x00000218 + 4 * (c)) -#define GSBI7_QUP_INPUT_FIFOc_REG(c) \ - (GSBI7_QUP7_REG_BASE + 0x00000218 + 4 * (c)) - -#define GSBI5_QUP_OUTPUT_FIFOc_REG(c) \ - (GSBI5_QUP5_REG_BASE + 0x00000110 + 4 * (c)) -#define GSBI6_QUP_OUTPUT_FIFOc_REG(c) \ - (GSBI6_QUP6_REG_BASE + 0x00000110 + 4 * (c)) -#define GSBI7_QUP_OUTPUT_FIFOc_REG(c) \ - (GSBI7_QUP7_REG_BASE + 0x00000110 + 4 * (c)) - -#define GSBI5_QUP_MX_INPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000200) -#define GSBI6_QUP_MX_INPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000200) -#define GSBI7_QUP_MX_INPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000200) - -#define GSBI5_QUP_MX_OUTPUT_COUNT_REG (GSBI5_QUP5_REG_BASE + 0x00000100) -#define GSBI6_QUP_MX_OUTPUT_COUNT_REG (GSBI6_QUP6_REG_BASE + 0x00000100) -#define GSBI7_QUP_MX_OUTPUT_COUNT_REG (GSBI7_QUP7_REG_BASE + 0x00000100) - -#define GSBI5_QUP_SW_RESET_REG (GSBI5_QUP5_REG_BASE + 0x0000000c) -#define GSBI6_QUP_SW_RESET_REG (GSBI6_QUP6_REG_BASE + 0x0000000c) -#define GSBI7_QUP_SW_RESET_REG (GSBI7_QUP7_REG_BASE + 0x0000000c) - -#define CLK_CTL_REG_BASE 0x00900000 -#define GSBIn_RESET_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029dc + 32 * ((n)-1)) - -#define SFAB_AHB_S3_FCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x0000216c) -#define CFPB_CLK_NS_REG \ - (CLK_CTL_REG_BASE + 0x0000264c) -#define SFAB_CFPB_S_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x000026c0) -#define CFPB_SPLITTER_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x000026e0) -#define CFPB0_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x00002650) -#define CFPB2_HCLK_CTL_REG \ - (CLK_CTL_REG_BASE + 0x00002658) -#define GSBIn_HCLK_CTL_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029c0 + 32 * ((n)-1)) -#define GSBIn_QUP_APPS_NS_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029cc + 32 * ((n)-1)) -#define GSBIn_QUP_APPS_MD_REG(n) \ - (CLK_CTL_REG_BASE + 0x000029c8 + 32 * ((n)-1)) -#define CLK_HALT_CFPB_STATEB_REG \ - (CLK_CTL_REG_BASE + 0x00002fd0) - -#define GSBI5_HCLK 23 -#define GSBI6_HCLK 19 -#define GSBI7_HCLK 15 -#define GSBI5_QUP_APPS_CLK 20 -#define GSBI6_QUP_APPS_CLK 16 -#define GSBI7_QUP_APPS_CLK 12 -#define GSBI_CLK_BRANCH_ENA_MSK (1 << 4) -#define GSBI_CLK_BRANCH_ENA (1 << 4) -#define GSBI_CLK_BRANCH_DIS (0 << 4) -#define QUP_CLK_BRANCH_ENA_MSK (1 << 9) -#define QUP_CLK_BRANCH_ENA (1 << 9) -#define QUP_CLK_BRANCH_DIS (0 << 9) -#define CLK_ROOT_ENA_MSK (1 << 11) -#define CLK_ROOT_ENA (1 << 11) -#define CLK_ROOT_DIS (0 << 11) - -#define QUP_STATE_VALID_BIT 2 -#define QUP_STATE_VALID 1 -#define QUP_STATE_MASK 0x3 -#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) -#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) -#define SPI_QUP_CONF_INPUT_MSK (1 << 7) -#define SPI_QUP_CONF_INPUT_ENA (0 << 7) -#define SPI_QUP_CONF_NO_INPUT (1 << 7) -#define SPI_QUP_CONF_OUTPUT_MSK (1 << 6) -#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) -#define SPI_QUP_CONF_NO_OUTPUT (1 << 6) -#define SPI_QUP_CONF_OUTPUT_ENA (0 << 6) -#define QUP_STATE_RESET_STATE 0x0 -#define QUP_STATE_RUN_STATE 0x1 -#define QUP_STATE_PAUSE_STATE 0x3 -#define SPI_BIT_WORD_MSK 0x1F -#define SPI_8_BIT_WORD 0x07 -#define PROTOCOL_CODE_MSK (0x07 << 4) -#define PROTOCOL_CODE_SPI (0x03 << 4) -#define LOOP_BACK_MSK (1 << 8) -#define NO_LOOP_BACK (0 << 8) -#define SLAVE_OPERATION_MSK (1 << 5) -#define SLAVE_OPERATION (0 << 5) -#define CLK_ALWAYS_ON (0 << 9) -#define MX_CS_MODE (0 << 8) -#define NO_TRI_STATE (1 << 0) -#define OUTPUT_BIT_SHIFT_MSK (1 << 16) -#define OUTPUT_BIT_SHIFT_EN (1 << 16) -#define INPUT_BLOCK_MODE_MSK (0x03 << 12) -#define INPUT_BLOCK_MODE (0x01 << 12) -#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10) -#define OUTPUT_BLOCK_MODE (0x01 << 10) -#define GSBI1_RESET (1 << 0) -#define GSBI1_RESET_MSK 0x1 - -#define GSBI_M_VAL_SHFT 16 -#define GSBIn_M_VAL_MSK (0xFF << GSBI_M_VAL_SHFT) -#define GSBI_N_VAL_SHFT 16 -#define GSBIn_N_VAL_MSK (0xFF << GSBI_N_VAL_SHFT) -#define GSBI_D_VAL_SHFT 0 -#define GSBIn_D_VAL_MSK (0xFF << GSBI_D_VAL_SHFT) -#define MNCNTR_RST_MSK (1 << 7) -#define MNCNTR_RST_ENA (1 << 7) -#define MNCNTR_RST_DIS (0 << 7) -#define MNCNTR_MSK (1 << 8) -#define MNCNTR_EN (1 << 8) -#define MNCNTR_DIS (0 << 8) -#define MNCNTR_MODE_MSK (0x3 << 5) -#define MNCNTR_MODE_BYPASS (0 << 5) -#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5) -#define GSBI_PRE_DIV_SEL_SHFT 3 -#define GSBIn_PRE_DIV_SEL_MSK (0x3 << GSBI_PRE_DIV_SEL_SHFT) -#define GSBIn_PLL_SRC_MSK (0x03 << 0) -#define GSBIn_PLL_SRC_PXO (0 << 0) -#define GSBIn_PLL_SRC_PLL8 (0x3 << 0) - -#define SPI_INPUT_FIRST_MODE (1 << 9) -#define SPI_IO_CONTROL_CLOCK_IDLE_HIGH (1 << 10) -#define QUP_DATA_AVAILABLE_FOR_READ (1 << 5) -#define QUP_OUTPUT_FIFO_NOT_EMPTY (1 << 4) -#define OUTPUT_SERVICE_FLAG (1 << 8) -#define INPUT_SERVICE_FLAG (1 << 9) -#define QUP_OUTPUT_FIFO_FULL (1 << 6) -#define QUP_INPUT_FIFO_NOT_EMPTY (1 << 5) -#define SPI_INPUT_BLOCK_SIZE 4 -#define SPI_OUTPUT_BLOCK_SIZE 4 -#define GSBI5_SPI_CLK 21 -#define GSBI5_SPI_MISO 19 -#define GSBI5_SPI_MOSI 18 -#define GSBI5_SPI_CS_0 20 -#define GSBI5_SPI_CS_1 61 -#define GSBI5_SPI_CS_2 62 -#define GSBI5_SPI_CS_3 2 -#define GSBI6_SPI_CLK 30 -#define GSBI6_SPI_CS_0 29 -#define GSBI6_SPI_MISO 28 -#define GSBI6_SPI_MOSI 27 -#define GSBI7_SPI_CLK 9 -#define GSBI7_SPI_CS_0 8 -#define GSBI7_SPI_MISO 7 -#define GSBI7_SPI_MOSI 6 - -#define MSM_GSBI_MAX_FREQ 51200000 - -#define SPI_RESET_STATE 0 -#define SPI_RUN_STATE 1 -#define SPI_PAUSE_STATE 3 -#define SPI_CORE_RESET 0 -#define SPI_CORE_RUNNING 1 -#define GSBI_SPI_MODE_0 0 -#define GSBI_SPI_MODE_1 1 -#define GSBI_SPI_MODE_2 2 -#define GSBI_SPI_MODE_3 3 -#define GSBI5_SPI 0 -#define GSBI6_SPI 1 -#define GSBI7_SPI 2 - -struct gsbi_spi { - unsigned int spi_config; - unsigned int io_control; - unsigned int error_flags; - unsigned int error_flags_en; - unsigned int gsbi_ctrl; - unsigned int qup_config; - unsigned int qup_error_flags; - unsigned int qup_error_flags_en; - unsigned int qup_operational; - unsigned int qup_io_modes; - unsigned int qup_state; - unsigned int qup_input_fifo; - unsigned int qup_output_fifo; - unsigned int qup_mx_input_count; - unsigned int qup_mx_output_count; - unsigned int qup_sw_reset; - unsigned int qup_ns_reg; - unsigned int qup_md_reg; -}; - -struct ipq_spi_slave { - struct spi_slave slave; - const struct gsbi_spi *regs; - unsigned int mode; - unsigned int initialized; - unsigned long freq; - int allocated; -}; - -static inline struct ipq_spi_slave *to_ipq_spi(struct spi_slave *slave) -{ - return container_of(slave, struct ipq_spi_slave, slave); -} - -#endif /* _IPQ_SPI_H_ */ diff --git a/src/soc/qualcomm/ipq806x/include/usb.h b/src/soc/qualcomm/ipq806x/include/usb.h deleted file mode 100644 index c3c4c48..0000000 --- a/src/soc/qualcomm/ipq806x/include/usb.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _IPQ806X_USB_H_ -#define _IPQ806X_USB_H_ - -void setup_usb_host1(void); -void setup_usb_host2(void); - -#endif /* _IPQ806X_USB_H_ */ diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld deleted file mode 100644 index 3059603..0000000 --- a/src/soc/qualcomm/ipq806x/memlayout.ld +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -/* TODO: This should be revised by someone who understands the SoC better. */ - -SECTIONS -{ - /* TODO: add SRAM_START(), SRAM_END() and REGION(reserved_sbl) */ - TTB(0x2A05C000, 48K) - - DRAM_START(0x40000000) - CBFS_CACHE(0x405CC000, 192K) - STACK(0x405FC000, 16K) - /* TODO: "256K bytes left for TZBSP"... what does that mean? */ - BOOTBLOCK(0x40600000, 32K) - PRERAM_CBMEM_CONSOLE(0x40618000, 8K) - ROMSTAGE(0x40620000, 128K) - RAMSTAGE(0x40640000, 128K) - DMA_COHERENT(0x5A000000, 2M) -} diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 54d54b2..4cf64eb 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -4,11 +4,11 @@
#include <arch/io.h> #include <delay.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/spi.h> #include <stdlib.h> #include <string.h> -#include <spi.h> -#include <gpio.h> -#include <iomap.h>
#define SUCCESS 0
diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c index 55386e9..f52f2ef 100644 --- a/src/soc/qualcomm/ipq806x/timer.c +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -29,8 +29,8 @@ */
#include <delay.h> -#include <iomap.h> -#include <ipq_timer.h> +#include <soc/iomap.h> +#include <soc/ipq_timer.h> #include <timer.h>
/* diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 4989247..3e8e187 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -34,12 +34,12 @@ #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <delay.h> -#include <clock.h> -#include <gpio.h> -#include <gsbi.h> #include <console/uart.h> -#include <ipq_uart.h> +#include <delay.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/gsbi.h> +#include <soc/ipq_uart.h> #include <stdint.h> #include <stdlib.h>
diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index a9214be..fb89373 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -17,13 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <delay.h> #include <arch/io.h> #include <console/console.h> - -#include "clock.h" -#include "iomap.h" -#include "usb.h" +#include <delay.h> +#include <soc/clock.h> +#include <soc/iomap.h> +#include <soc/usb.h>
#define CRPORT_TX_OVRD_DRV_LO 0x1002 #define CRPORT_RX_OVRD_IN_HI 0x1006
-
Patrick Georgi