Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 )

Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
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Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/33759/9/src/soc/amd/picasso/reset_v... 
File src/soc/amd/picasso/reset_vector.S:

https://review.coreboot.org/c/coreboot/+/33759/9/src/soc/amd/picasso/reset_v... 
PS9, Line 111: 	.byte	0x00, 0x9b, 0xaf, 0x00
> Do we need a romstage larger than 64KiB? If so, we can re-jigger that bit for bootblock too to ensur […]

So far I haven't needed it bigger than 64K but I specifically gave myself the option.  Since FSP-M is its own separate cbfs file I still have over 27,000 bytes left.

Being explicit is probably a nice-to-have for all scenarios vs. assume 64K is always the max.  I don't see it as a gating requirement though.